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FS6131-01
FS6131-01
FS6131-01
FS6131-01
Programmable Line Lock Clock Generator IC
Programmable Line Lock Clock Generator IC
Programmable Line Lock Clock Generator IC
Programmable Line Lock Clock Generator IC
Table 18: Serial Interface Timing Specifications
Unless otherwise stated, VDD = 5.0V ± 10%, no load on any output, and ambient temperature range TA = 0°C to 70°C. Parameters denoted with an asterisk ( * ) represent nominal characterization
data and are not production tested to any specific limits. MIN and MAX characterization data are
± 3σ from typical.
STANDARD MODE
PARAMETER
SYMBOL
CONDITIONS/DESCRIPTION
MIN.
MAX.
UNITS
Clock frequency
fSCL
SCL
0
400
kHz
Bus free time between STOP and START
tBUF
4.7
µs
Set up time, START (repeated)
tsu:STA
4.7
µs
Hold time, START
thd:STA
4.0
µs
Set up time, data input
tsu:DAT
SDA
250
ns
Hold time, data input
thd:DAT
SDA
0
µs
Output data valid from clock
tAA
Minimum delay to bridge undefined region of the falling
edge of SCL to avoid unintended START or STOP
3.5
µs
Rise time, data and clock
tR
SDA, SCL
1000
ns
Fall time, data and clock
tF
SDA, SCL
300
ns
High time, clock
tHI
SCL
4.0
µs
Low time, clock
tLO
SCL
4.7
µs
Set up time, STOP
tsu:STO
4.0
µs
Figure 17: Bus Timing Data
SCL
SDA
STOP
t
su:STO
t
hd:STA
START
t
su:STA
ADDRESS OR
DATA VALID
DATA CAN
CHANGE
Figure 18: Data Transfer Sequence
SCL
SDA
IN
t
hd:DAT
t
hd:STA
t
su:STA
t
su:STO
t
LO
t
HI
SDA
OUT
t
su:DAT
t
BUF
t
R
t
F
t
AA
t
AA
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