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M41T83RM6F Datasheet(PDF) 36 Page - STMicroelectronics |
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M41T83RM6F Datasheet(HTML) 36 Page - STMicroelectronics |
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36 / 58 page  Clock operation M41T82 M41T83 36/58 3.6 Optional second programmable alarm When the Alarm 2 Enable (AL2E) bit (D1 of address 13h) is set to a logic ‘1’, registers 14h through 18h provide control for a second programmable alarm which operates in the same manner as the alarm function described above. The A2IE (Alarm 2 Interrupt Enable) bit allows the second alarm to trigger a separate interrupt output (IRQ2). The AL2E bit defaults on initial power-up to a logic ‘0’ (Alarm 2 disabled). In this mode, the five address bytes (14h-18h) function as additional user SRAM, for a total of 12 bytes of user SRAM. The IRQ1/FT/OUT pin can also be activated in the battery back-up mode (see Figure 22 on page 36). Figure 21. Alarm interrupt reset waveform Figure 22. Back-up mode alarm waveform 1. ABE and A1IE bits = 1. ALARM FLAG BITS (AFx) 0Fh 0Eh 00h HIGH-Z AI08898 IRQ1/FT/OUT or IRQ2 VCC IRQ1/FT/OUT or IRQ2 AF Bit in Flags Register HIGH-Z VSO VPFD trec AI09164c |
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