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M34C02-LMB1G Datasheet(PDF) 20 Page - STMicroelectronics |
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M34C02-LMB1G Datasheet(HTML) 20 Page - STMicroelectronics |
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20 / 31 page ![]() Initial delivery state M34C02-W, M34C02-L, M34C02-R 20/31 5 Initial delivery state The device is delivered with all bits in the memory array set to 1 (each Byte contains FFh). Figure 11. Serial presence detect block diagram 1. E0, E1 and E2 are wired at each DIMM socket in a binary sequence for a maximum of 8 devices. 2. Common clock and common data are shared across all the devices. 3. Pull-up resistors are required on all SDA and SCL bus lines (typically 4.7 k Ω) because these lines are open drain when used as outputs. R = 4.7k Ω AI01937 DIMM Position 7 SDA SCL E0 E1 E2 VCC DIMM Position 6 SDA SCL E0 E1 E2 DIMM Position 5 SDA SCL E0 E1 E2 DIMM Position 4 SDA SCL E0 E1 E2 DIMM Position 3 SDA SCL E0 E1 E2 DIMM Position 2 SDA SCL E0 E1 E2 VCC DIMM Position 1 SDA SCL E0 E1 E2 DIMM Position 0 SDA SCL E0 E1 E2 VSS VSS VSS VCC VSS VSS VCC VCC VSS VCC VCC VSS VSS VCC SCL line SDA line From the motherboard I2C master controller |
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