CSTCC10.0MGA datasheet(144/153 Pages) STMICROELECTRONICS

144 / 153 page

ST72334J/N, ST72314J/N, ST72124J

144/153

18 DEVICE CONFIGURATION AND ORDERING INFORMATION

Each device is available for production in user pro-

grammable versions (FLASH) as well as in factory

coded versions (ROM). E2PROM data memory

and FLASH devices are shipped to customers with

a default content (FFh), while ROM factory coded

parts contain the code supplied by the customer.

This implies that FLASH devices have to be con-

figured by the customer using the Option Bytes

while the ROM devices are factory-configured.

18.1 OPTION BYTES

The two option bytes allow the hardware configu-

ration of the microcontroller to be selected.

The option bytes have no address in the memory

map and can be accessed only in programming

mode (for example using a standard ST7 program-

ming tool). The default content of the FLASH is

fixed to FFh.

In masked ROM devices, the option bytes are

fixed in hardware by the ROM code (see option

list).

USER OPTION BYTE 0

Bit 7:2 = Reserved, must always be 1.

Bit 1 = 56/42

Package Configuration.

This option bit allows to configured the device ac-

cording to the package.

0: 42 or 44 pin packages

1: 56 or 64 pin packages

Bit 0 = FMP

Full memory protection.

This option bit enables or disables external access

to the internal program memory (read-out protec-

tion). Clearing this bit causes the erasing (by over-

writing with the currently latched values) of the

whole memory (not including the option bytes).

0: Program memory not read-out protected

1: Program memory read-out protected

Note: The data E2PROM is not protected by this

bit in flash devices. In ROM devices, a protection

can be selected in the Option List (see page 146).

USER OPTION BYTE 1

Bit 7 = CSS

Clock Security System disable

This option bit enables or disables the CSS fea-

tures.

0: CSS enabled

1: CSS disabled

Bit 6:4 = OSC[2:0]

Oscillator selection

These three option bits can be used to select the

main oscillator as shown in Table 24.

Bit 3:2 = LVD[1:0]

Low voltage detection selection

These option bits enable the LVD block with a se-

lected threshold as shown in Table 25.

Bit 1 = WDG HALT

Watchdog Reset on HALTt

mode

This option bit determines if a RESET is generated

when entering HALT mode while the Watchdog is

active.

0: No Reset generation when entering Halt mode

1: Reset generation when entering Halt mode

Bit 0 = WDG SW

Hardware or software watchdog

This option bit selects the watchdog type.

0: Hardware (watchdog always enabled)

1: Software (watchdog to be enabled by software)

Table 24. Main Oscillator Configuration

Table 25. LVD Threshold Configuration

Selected Oscillator

OSC2 OSC1 OSC0

External Clock (Stand-by)

~4 MHz Internal RC

1~14 MHz External RC

Low Power Resonator (LP)

Medium Power Resonator (MP)

Medium Speed Resonator (MS)

High Speed Resonator (HS)

Configuration

LVD1 LVD0

LVD Off

Highest Voltage Threshold (

∼4.50V)

Medium Voltage Threshold (

∼4.05V)

Lowest Voltage Threshold (

∼3.45V)

USER OPTION BYTE 0

USER OPTION BYTE 1

Reserved

56/42 FMP

CSS

OSC

LVD1 LVD0

WDG

HALT

WDG

Default

Value

111111

1101

111

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