CST12.0MTWA datasheet(78/153 Pages) STMICROELECTRONICS

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SERIAL PERIPHERAL INTERFACE (Cont’d)

14.4.4.4 Write Collision Error

A write collision occurs when the software tries to

write to the DR register while a data transfer is tak-

ing place with an external device. When this hap-

pens, the transfer continues uninterrupted; and

the software write will be unsuccessful.

Write collisions can occur both in master and slave

mode.

Note: a "read collision" will never occur since the

received data byte is placed in a buffer in which

access is always synchronous with the MCU oper-

ation.

In Slave mode

When the CPHA bit is set:

The slave device will receive a clock (SCK) edge

prior to the latch of the first data transfer. This first

clock edge will freeze the data in the slave device

DR register and output the MSBit on to the exter-

nal MISO pin of the slave device.

The SS pin low state enables the slave device but

the output of the MSBit onto the MISO pin does

not take place until the first data transfer clock

edge.

When the CPHA bit is reset:

Data is latched on the occurrence of the first clock

transition. The slave device does not have any

way of knowing when that transition will occur;

therefore, the slave device collision occurs when

software attempts to write the DR register after its

SS pin has been pulled low.

For this reason, the SS pin must be high, between

each data byte transfer, to allow the CPU to write

in the DR register without generating a write colli-

sion.

In Master mode

Collision in the master device is defined as a write

of the DR register while the internal serial clock

(SCK) is in the process of transfer.

The SS pin signal must be always high on the

master device.

WCOL bit

The WCOL bit in the SR register is set if a write

collision occurs.

No SPI interrupt is generated when the WCOL bit

is set (the WCOL bit is a status flag only).

Clearing the WCOL bit is done through a software

sequence (see Figure 46).

Figure 46. Clearing the WCOL bit (Write Collision Flag) Software Sequence

Clearing sequence after SPIF = 1 (end of a data byte transfer)

1st Step

Read SR

Read DR

Write DR

2nd Step

SPIF =0

WCOL=0

SPIF =0

WCOL=0 if no transfer has started

WCOL=1 if a transfer has started

Clearing sequence before SPIF = 1 (during a data byte transfer)

1st Step

2nd Step

WCOL=0

before the 2nd step

Read SR

Read DR

Note: Writing to the DR register

instead of reading in it does not

reset the WCOL bit

Read SR

THEN

CST12.0MTWA Datasheet(PDF) 78 Page - STMicroelectronics

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