M61048FP

Rev.1.00 Mar 04, 2005 page 2 of 23

Pin Arrangement

(Top view)

Package: PLSP0020JB-A (20P2F-A)

1

2

3

4

5

6

7

8

9

10

20

19

18

17

16

15

14

13

12

11

CS

CFETCNT

VIN1

VIN2

VIN3

VIN4

RESET

VIN12

N.C.

DFETCNT

CK

DI

ANALOG

CFET

DFET

PCFET

GND

VREG

N.C.

VCC

Pin Description

Pin No.

Pin Name

Function

10

VCC

Power source pin. Power from charger or battery

8

VREG

Linear-Regulator output for microcomputer

13

VIN12

Monitoring charger is connected or not

18

VIN1

Battery 1 + voltage input

17

VIN2

Battery 1 – voltage and Battery 2 + voltage input

16

VIN3

Battery 2 – voltage and Battery 3 + voltage input

15

VIN4

Battery 3 – voltage and Battery 4 + voltage input

7

GND

Ground and Battery 4 - voltage input

5

DFET

Discharge FET-Drive Output. The Driver is turned off by Microcomputer

4

CFET

Charge FET-Drive Output. The Driver is turned off by Microcomputer

6

PCFET

Pre-charge FET-Drive Output. The Driver is turned off by Microcomputer

14

RESET

Reset signal output to RESET of Microcomputer

3

ANALOG

Various Analog signal outputs to AD-input of Microcomputer

19

CFETCNT

Input of CFET and PCFET control signal from Microcomputer

11

DFETCNT

Input of DFET control signal from Microcomputer

20

CS

During low signal input to this CS, data input to DI is enabled

1

CK

Input of shift clock from Microcomputer. DI's input data is latched by low-to-high edge of this CK

2

DI

Input of 6-bit length serial data from Microcomputer