MAQ430 – 12-BIT, AUTOMOTIVE ANGLE SENSOR WITH ABZ & UVW OUTPUTS

MAQ430 Rev. 1.2

MonolithicPower.com

11

8/8/2022

MPS Proprietary Information. Patent Protected. Unauthorized Photocopy and Duplication Prohibited.

© 2022 MPS. All Rights Reserved.

Figure 4: End-of-Shaft Mounting

If the end-of-shaft position is not available, the

sensor can be positioned away from the

rotation axis of a cylinder or ring magnet (see

Figure 5). In this case, the magnetic field angle

is

no

longer

directly

proportional

to

the

mechanical

angle.

The

MAQ430

can

be

adjusted to compensate for this effect and

recover

the

linear

relation

between

the

mechanical angle and the sensor output. With

multiple

pole

pair

magnets,

the

MAQ430

indicates multiple rotations for each mechanical

turn.

Figure 5: Side-Shaft Mounting

Electrical Mounting and Power Supply

Decoupling

It is recommended to place a 1µF decoupling

capacitor close to the sensor with a low

impedance path to GND (see Figure 6).

Figure 6: Connection for Supply Decoupling

Generally, the MagAlpha works fine with or

without the exposed pad connected to anything.

For optimum conditions (electrically, thermally,

and mechanically), it is recommended that the

exposed pad be connected to ground.

Serial Interface

The sensor supports the SPI serial interface for

angle reading and register programming.

SPI

SPI

is

a

4-wire,

synchronous,

serial

communication

interface.

The

MagAlpha

supports SPI Mode 3 and Mode 0 (see Table 1

and Table 2). The SPI Mode (0 or 3) is detected

automatically by the sensor and therefore does

not require any action from the user. The

maximum clock rate supported on SPI is

25MHz. There is no minimum clock rate. Note

that real life data rates depend on PCB layout

quality and signal trace length. See Figure 7,

Figure 8, and Table 3 for SPI timing.

All commands to the MagAlpha (whether for

writing or reading register content) must be

transferred through the SPI MOSI pin and must

be 16 bits long.

For checking the integrity of the data received

(angle or register content) the master shall send

a 17th clock count and receive a parity bit.

See the SPI Communication section on page

13 for details.

Table 1: SPI Specification

Mode 0

Mode 3

SCLK idle state

Low

High

Data capture

On SCLK rising edge

Data transmission

On SCLK falling edge

CS idle state

High

Data order

MSB first

Table 2: SPI Standard

Mode 0

Mode 3

CPOL

0

1

CPHA

0

1

Data order (DORD)

0 (MSB first)