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ES9027SPRO Datasheet(PDF) 64 Page - ESS Technology,Inc |
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ES9027SPRO Datasheet(HTML) 64 Page - ESS Technology,Inc |
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64 / 89 page  ES9027PRO Datasheet VERSION 0.4.1 ESS TECHNOLOGY, INC. 109 Bonaventura Drive, San Jose, CA 95134, USA Tel (408) 643-8800 • WWW.ESSTECH.COM 64 Register 59: TDM CONFIG Bits [7:5] [4:0] Default 3'd0 5'd1 Bits Mnemonic Description [7:5] RESERVED NA [4:0] TDM_CH_NUM Total number of TDM slots per frame = TDM_CH_NUM + 1. Register 60: TDM CONFIG1 Bits [7] [6] [5:0] Default 1'b0 1'b0 6'd0 Bits Mnemonic Description [7] TDM_LJ_MODE TDM LJ mode. • 1'b0: Standard I2S (default) • 1'b1: LJ mode [6] TDM_VALID_EDGE TDM WS valid edge. • 1'b0: negative edge (default) • 1'b1: positive edge [5:0] RESERVED NA Register 61: TDM CONFIG2 Bits [7] [6:5] [4:0] Default 1'b1 2'b00 5'd0 Bits Mnemonic Description [7] ENABLE_ASYNC_LOCK_MONITOR Monitors the lock status of the SRC, when in ASYNC mode. Sets BCK_WS_FAIL on unlock. • 1'b0: Disabled • 1'b1: Enabled (default) [6:5] TDM_BIT_WIDTH Bit width of each TDM slot. • 2'b00: 32-bit (default) • 2'b01: 24-bit • 2'b10: 16-bit • 2'b11: Reserved [4:0] TDM_DATA_LATCH_ADJ Sets the position of the start bit within each TDM slot. Can be moved by TDM_DATA_LATCH_ADJ clock cycles. • 5'd0: Normal position • 5'd1-31: Number of clock cycles to wait |
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