TC1270AMAVRCTR datasheet(18/42 Pages) MICROCHIP

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TC1270A/70AN/71A

DS20002035F-page 18

 2007-2022 Microchip Technology Inc. and its subsidiaries

If the VDD is rising as it crosses the VTRIP voltage, the

RST/RST pin is driven inactive after the Reset Delay

Timer elapses. Then, the desired circuitry is released

from Reset and will start to operate in its Normal mode,

or the circuitry has the indication that the VDD is above

the selected VTRIP.

TABLE 4-2:

SELECTING THE TRIP POINT

The

TC1270A/TC1270AN/TC1271A

devices

are

optimized to reject fast transient glitches on the VDD

line. If the low input signal (which is below VTRIP) is not

rejected, the Reset output is driven active within 50 µs

of VDD falling through the Reset voltage threshold.

After the device exits the Reset condition, the delay

circuitry will hold the RST/RST pin active until the

appropriate Reset delay time (tRST) has elapsed.

During device power-up, the input voltage is below the

trip point voltage. The device must enter the valid oper-

ating range for the device to start operation.

4.2.1

HYSTERESIS

There is also a minimal hysteresis (VHYS) on the trip

point. This is so that small noise signals on the device

voltage (VDD) do not cause the Reset pin (RST/RST) to

“jitter” (oscillate between active and inactive levels).

The characterization graphs shown in Figures 2-13

through 2-15 show the device hysteresis as a

percentage of the voltage trip point (VTRIP).

The Reset Delay Timer (tRST) gives a time-based

hysteresis for the system.

4.2.2

POWER-UP/RISING VDD

As the device VDD rises, the device’s Reset circuit will

remain active until the voltage rises above the “actual”

trip point (VTRIP).

Figure 4-7 shows a power-up sequence and the

waveform of the RST and RST pins. As the device

powers up, the voltage will start below the valid

operating voltage of the device. At this voltage, the

RST/RST output is not valid. Once the voltage is above

the minimum operating voltage (1V) and below the

selected VTRIP, the Reset output will be active.

Once the device voltage rises above the VTRIP voltage,

the Reset Delay Timer (tRST) starts. When the Reset

Delay Timer times out, the Reset output (RST/RST) is

driven inactive.

FIGURE 4-7:

RST/RST Pin Operation

Power-up.

4.2.3

POWER-DOWN/BROWN-OUT

As the device powers-down/browns-out, the VDD falls

from a voltage above the devices trip point (VTRIP). The

device will trip at a voltage between the maximum trip

point (VTRIP(MAX)) and the minimum trip point

(VTRIP(MIN)). Once the device voltage (VDD) goes

below this voltage, the RST/RST pin will be forced to

the active state. Table 4-3 shows the state of the RST

or RST pins.

Figure 4-8 shows the waveform of the RST pin as

determined by the VDD voltage. As the VDD voltage falls

from the normal operating point, the device “enters”

Reset by crossing the VTRIP voltage (between

VTRIP(MAX) and VTRIP(MIN)). Then, when VDD voltage

rises, the device “exits” Reset by crossing the VTRIP

voltage (below, or at, VTRIP(MAX)). After the “exit” state

Trip

Voltage

Selection

VTRIP(MAX)(1)/

VTRIP(MIN)(2)

- % From

Regulated Voltage

5.0V

3.3V

3.0V

4.75V

5.0%

—

4.50V

10.0%

—

M4.50V

10.0%

—

4.25V

15.0%

—

3.15V

—

4.5%

—

3.00V

—

9.2%

—

3.00V

—

9.2%

—

2.85V

—

13.7%

—

R2.70V

—

10.0%

2.55V

—

15.0%

Note 1: Voltage regulator circuit must have tighter

tolerance (%) than VTRIP(MAX)% from

regulated voltage.

2: Circuitry being reset must have a wider

tolerance (%) than VTRIP(MIN)% from

regulated voltage.

VTRIP

VDD

tRST(1)

RST(2)

RST

Note 1: Additional system current is consumed

during the tRST time.

2: The TC1270AN requires an external

pull-up resistor.

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