AD9549 datasheet(31/78 Pages) AD

31 / 78 page

Preliminary Technical Data

AD9549

Rev. PrA | Page 31 of 78

For example, suppose that FPFD_Gain=200, fCLK=3MHz, and 1°

of phase offset is desired. First, we must find the value of

∆t

OFFSET

, which is:

()

MHz

CLK

OFFSET

925

360

deg

∆

Having determined ∆tOFFSET, we have:

(

) 1896

200

925

⋅

PLL

OFFSET

The result has been rounded because PLLOFFSET is restricted to

integer values.

NOTE: The PLLOFFSET value is programmed as a 14-bit, twos-

complement number. However, the user must ensure that the

magnitude is constrained to 12 bits, such that:

-211 ≤ PLLOFFSET < +211

The above constraint yields a timing adjustment range of ±1ns.

This ensures that the phase offset remains within the bounds of

the fine phase detector.

LOCK DETECTION

Phase Lock Detection

During the phase locking process, the output of the phase

detector tends toward a value of zero, which indicates perfect

alignment of the phase detector input signals. As the control

loop works to maintain the alignment of the phase detector

input signals, the output of the phase detector wanders around

zero.

The phase lock detector tracks the absolute value of the digital

samples generated by the phase detector. These samples are

compared to the Phase Lock Detect Threshold value

programmed in the I/O Register Map. A false state at the

output of the comparator indicates the absolute value of a

sample exceeds the value in the threshold register. A true state

at the output of the comparator indicates alignment of the phase

detector input signals to the degree specified by the lock

detection threshold.

Digital

Comparator

Phase

Lock

Detect

Absolute

Value

P-Divider Clock

Phase

Detector

Samples

Control Logic

Lock

Timer

Unlock

Timer

I/O Registers

Loop

RESET

Phase Lock Detect

Threshold

Figure 15: Phase Lock Detector Block Diagram

The Phase Lock Detect Threshold value (PLDT) is a 32-bit

number stored in the I/O Register Map:

(

)

Gain

FPFD

round

PLDT

⋅

∆

Where ∆t is the maximum allowable timing error between the

signals at the input to the phase detector and the value of

FPFD_Gain is as described in the Fine Phase Detector section.

For example, suppose that fR/R=3MHz, FPFD_Gain=200, and

the maximum timing deviation is given as 1°. This yields a ∆t

value of:

(

)

()6

360

⋅

∆

The resulting phase lock detect threshold is:

() 1896

360

200













⋅

= round

PLDT

Hence, 1896 (00000768h) is the value that must be stored in the

Phase Lock Detect Threshold register.

The "phase lock detect" signal is generated once the control

logic observes that the output of the comparator has been in the

true state for 2X periods of the P-Divider clock (see the Digital

Loop Filter section for a description of the P-Divider). Once the

phase lock detect signal is asserted, it remains asserted until

cleared by an "unlock" event or by a device RESET.

The duration of the lock detection process is programmable via

the Phase Lock Watchdog Timer register. The interval is

controlled by a 5-bit number, X (0 ≤ X ≤ 20). The absolute

duration of the phase lock detect interval is:

LOCK

AD9549 Datasheet(PDF) 31 Page - Analog Devices

AD9549 Datasheet(HTML) 31 Page - Analog Devices

Html Pages

1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 33 34 35 36 37 38 39 40 41 42 43 44 45 46 47 48 49 50 51 52 53 54 55 56 57 58 59 60 61 62 63 64 65 66 67 68 69 70 71 72 73 74 75 76 77 78

Datasheet Download

Link URL