M41T80

Clock operation

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3.5

Output driver pin

When the AFE Bit and SQWE Bit are not set, the IRQ/OUT/SQW pin becomes an output

driver that reflects the contents of D7 of the Control Register. In other words, when D7 (OUT

Bit) of address location 08h is a '0,' then the IRQ/OUT/SQW pin will be driven low.

Note:

The IRQ/OUT/SQW pin is an open drain which requires an external pull-up resistor.

3.6

Preferred power-on default

When powering the device up from ground (0V), the following register bits are set to a '0'

state: ST; AFE; and SQWE. The following bits are set to a '1' state: OUT and 32kE (see

Table 6: Preferred power-on default values on page 17).

Table 6.

Preferred power-on default values

Condition

ST

Out

AFE

SQWE

32kE

1.

01

0

0

1