WM8740

Production Data

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PD Rev 4.0 April 2004

13

REGISTER MAP

WM8740 controls the special functions using 4 program registers, which are 16-bits long. These

registers are all loaded through input pin MD/DM0. After the 16 data bits are clocked in, ML/I2S is

used to latch in the data to the appropriate register. Table 5 shows the complete mapping of the 4

registers. Note that in hardware differential mode and 8X modes, software control is not available.

The hardware differential mode (Diff[1:0]) clock loss detector disable (CDD) can only be accessed by

writing to M2[8:5] with the pattern 1111. Register M4 is then accessible by setting A[2:0] to 110.

B15

B14

B13

B12

B11

B10

B9

B8

B7

B6

B5

B4

B3

B2

B1

B0

M0

-

-

-

-

A2 (0) A1(0)

A0(0)

LDL

AL7

AL6

AL5

AL4

AL3

AL2

AL1

AL0

M1

-

-

-

-

A2(0)

A1(0)

A0(1)

LDR

AR7

AR6

AR5

AR4

AR3

AR2

AR1

AR0

M2

-

-

-

-

A2(0)

A1(1)

A0(0)

-

-

-

-

IW1

IW0

OPE

DEM

MUT

M3

-

-

-

-

A2(0)

A1(1)

A0(1)

IZD

SF1

SF0

-

REV

SR0

ATC

LRP

I

M4

-

-

-

-

A2(1)

A1(1)

A0(0)

-

-

CDD

DIFF1 DIFF0

-

-

-

-

Table 5 Mapping of Program Registers

REGISTER

BITS

NAME

DEFAULT

DESCRIPTION

[7:0]

AL[7:0]

FF

Attenuation data for left channel.

0

8

LDL

0

Attenuation data load control for left channel.

[7:0]

AR[7:0]

FF

Attenuation data for right channel.

1

8

LDR

0

Attenuation data load control for right channel.

0

MUT

0

Left and right DACs soft mute control.

1

DEM

0

De-emphasis control.

2

OPE

0

Left and right DACs operation control.

2

[4:3]

IW[1:0]

0

Input audio data bit select.

0

I2S

0

Audio data format select.

1

LRP

0

Polarity of LRCIN select.

2

ATC

0

Attenuator control.

3

SR0

0

Digital filter slow roll-off select.

4

REV

0

Output phase reverse.

[7:6]

SF[1:0]

0

Sampling rate select.

3

8

IZD

0

Infinite zero detection circuit control.

[5:4]

DIFF

0

Differential output mode.

4

6

CDD

0

Clock loss detector disable.

Table 6 Register Bit Descriptions

DAC OUTPUT ATTENUATION

The level of attenuation for eight bit code X, is given by:

0.5

∗ (X - 255) dB, 1 ≤ X ≤ 255

-

∞dB (mute),

X = 0

Bit 8 in register 0 (LDL) is used to control the loading of attenuation data in B[7:0]. When LDL is set

to 0, attenuation data will be loaded into AL[7:0], but it will not affect the filter attenuation. LDR in

register 1 has the same function for right channel attenuation. Only when LDL or LDR is set to '1' will

the filter attenuation be updated. This permits left and right channel attenuation to be updated

simultaneously.

Attenuation level is controlled by AL[7:0] (left channel) or AR[7:0] (right channel). Attenuation levels

are given in Table 7.