AD8021 datasheet(20/28 Pages) AD

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AD8021

Rev. F | Page 20 of 28

CF = CL = 0, RL = 1 kΩ, RIN = 49.9 Ω (see Figure 49).

Table 6. Recommended Component Values

Noise Gain

(Noninverting

Gain)

RS (Ω)

RF (Ω)

RG (Ω)

CCOMP (pF)

Slew Rate (V/μs)

−3 dB

SS BW

(MHz)

Output Noise

(AD8021 Only)

(nV/√Hz)

Output Noise

(AD8021 with Resistors)

(nV/√Hz)

120

490

2.1

2.8

49.9

499

150

205

4.3

8.2

49.9

1 k

249

300

185

10.7

15.5

49.9

1 k

110

420

150

21.2

27.9

49.9

1 k

52.3

200

42.2

52.7

100

49.9

1 k

211.1

264.1

With the AD8021, a variety of trade-offs can be made to fine-

tune its dynamic performance. Sometimes more bandwidth

or slew rate is needed at a particular gain. Reducing the

compensation capacitance, as illustrated in Figure 7, increases

the bandwidth and peaking due to a decrease in phase margin.

On the other hand, if more stability is needed, increasing the

compensation capacitor decreases the bandwidth while

increasing the phase margin.

As with all high speed amplifiers, parasitic capacitance and

inductance around the amplifier can affect its dynamic

response. Often, the input capacitance (due to the op amp itself,

as well as the PC board) has a significant effect. The feedback

resistance, together with the input capacitance, can contribute

to a loss of phase margin, thereby affecting the high frequency

response, as shown in Figure 14. A capacitor (CF) in parallel

with the feedback resistor can compensate for this phase loss.

Additionally, any resistance in series with the source creates a

pole with the input capacitance (as well as dampen high

frequency resonance due to package and board inductance

and capacitance), the effect of which is shown in Figure 15.

It must also be noted that increasing resistor values increases

the overall noise of the amplifier and that reducing the feedback

resistor value increases the load on the output stage, thus

increasing distortion (see Figure 22).

USING THE DISABLE FEATURE

When Pin 8 (DISABLE) is higher than Pin 1 (LOGIC

REFERENCE) by approximately 2 V or more, the part is

enabled. When Pin 8 is brought down to within about 1.5 V

of Pin 1, the part is disabled. See Table 1 for exact disable and

enable voltage levels. If the disable feature is not used, Pin 8 can

be tied to VS or a logic high source, and Pin 1 can be tied to

ground or logic low. Alternatively, if Pin 1 and Pin 8 are not

connected, the part is in an enabled state.

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