BCM8021

®

10

-GbE XAUI™TRANSCEIVER WITH HIGH-SPEED REDUNDANCY

XAUI SerDes Application Diagram

• IEEE 802.3™ae-compliant XAUI™ to XGMII transceiver

• XAUI-to-XAUI retiming

• Less than 300 mW per transceiver channel including I/O

• Less than three picoseconds rms jitter generation

• Exceeds SONET jitter tolerance mask

transmit pre-emphasis

• Transmit pre-emphasis for interoperability with CML SerDes

• Receive equalization for copper interconnects

• Full loopback and on-chip PRBS generator/checker

• IEEE (1149.1) JTAG

• No requirement for heat sink or airflow

•

Advanced 0.13µ CMOS process technology provides

unparalleled performance while achieving the lowest possible

power consumption

•

IEEE 802.3ae 10-GbE physical coding sublayer (PCS) has a

selectable 8B/10B encoding/decoding block on-chip that can

be configured to support the 10-Gbps attachment unit

interface (XAUI)

•

Superior jitter characteristics enable the serializing/

deserializing (SerDes) of data signals transmitted through

front panel or backplane networking equipment supporting

both primary and protection circuits

•

Drive PMD devices or backplane directly with no external

clean-up circuit required

•

Simplifies manufacturability with integrated built-in self-test

(BIST), high-speed and low-speed loopbacks, and

programmable PRBS generator/checker

•

Decreases complexity and reduces board space on

multichannel linecard designs

FE A T UR E S

SU MM AR Y O F B E N E FI TS

APPL ICA T ION S

APPL I CATI O N S