AT83SND1CXXX-ROTIL datasheet(86/212 Pages) ATMEL

86 / 212 page

4109J–8051–10/06

AT8xC51SND1C

Warning 1: The Byte counter is not updated.

Warning 2: Do not write more Bytes than supported by the corresponding endpoint.

14.3.3

FIFO Mapping

Figure 14-8. Endpoint FIFO Configuration

14.4

Bulk/Interrupt Transactions

Bulk and Interrupt transactions are managed in the same way.

14.4.1

Bulk/Interrupt OUT Transactions in Standard Mode

Figure 14-9. Bulk/Interrupt OUT transactions in Standard Mode

An endpoint should be first enabled and configured before being able to receive Bulk or Interrupt

packets.

When a valid OUT packet is received on an endpoint, the RXOUTB0 bit is set by the USB con-

troller. This triggers an interrupt if enabled. The firmware has to select the corresponding

endpoint, store the number of data Bytes by reading the UBYCTX register. If the received packet

UEPNUM

Endpoint 0

Endpoint 2

UEPSTA0

UEPCON0

UEPDAT0

UEPSTA2

UEPCON2

UEPDAT2

SFR Registers

UEPSTAX

UEPCONX

UEPDATX

UBYCT0

UBYCT2

UBYCTX

OUT

DATA0 (n Bytes)

ACK

HOST

UFI

C51

Endpoint FIFO Read Byte 1

OUT

DATA1

NAK

RXOUTB0

Endpoint FIFO Read Byte 2

Endpoint FIFO Read Byte n

Clear RXOUTB0

OUT

DATA1

NAK

OUT

DATA1

ACK

RXOUTB0

Endpoint FIFO Read Byte 1

AT83SND1CXXX-ROTIL Datasheet(PDF) 86 Page - ATMEL Corporation

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