AT83SND1CXXX-ROTIL datasheet(101/212 Pages) ATMEL

101 / 212 page

101

4109J–8051–10/06

AT8xC51SND1C

Reset Value = 1000 0000b

Table 86. UEPSTAX Register

UEPSTAX (S:CEh) – USB Endpoint X Status and Control Register (X = EPNUM set in UEPNUM

)

Bit

Number

Bit

Mnemonic

Description

7EPEN

Endpoint Enable Bit

Set to enable the endpoint according to the device configuration. Endpoint 0

should always be enabled after a hardware or USB bus reset and participate in

the device configuration.

Clear to disable the endpoint according to the device configuration.

6NAKIEN

NAK Interrupt enable

Set this bit to enable NAK IN or NAK OUT interrupt.

Clear this bit to disable NAK IN or NAK OUT Interrupt.

5NAKOUT

NAK OUT received

This bit is set by hardware when an NAK handshake has been sent in response

of a OUT request from the Host. This triggers a USB interrupt when NAKIEN is

set.

This bit should be cleared by software.

4NAKIN

NAK IN received

This bit is set by hardware when an NAK handshake has been sent in response

of a IN request from the Host. This triggers a USB interrupt when NAKIEN is set.

This bit should be cleared by software.

3DTGL

Data Toggle Status Bit (Read-only)

Set by hardware when a DATA1 packet is received.

Cleared by hardware when a DATA0 packet is received.

2EPDIR

Endpoint Direction Bit

Set to configure IN direction for Bulk, Interrupt and Isochronous endpoints.

Clear to configure OUT direction for Bulk, Interrupt and Isochronous endpoints.

This bit has no effect for Control endpoints.

1-0

EPTYPE1:

Endpoint Type Bits

Set this field according to the endpoint configuration (Endpoint 0 should always

be configured as Control):

Control endpoint

Isochronous endpoint

Bulk endpoint

Interrupt endpoint

7654

3210

DIR

RXOUTB1

STALLRQ

TXRDY

STLCRC

RXSETUP

RXOUTB0

TXCMP

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