BL702SLASH704SLASH706 datasheet(13/47 Pages) BOUFFALOALB

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BL702/704/706 Datasheet

Table 2.2: Memory Map

Module

Base Address

Size

Description

ROM

0x21000000

192KB

Read-only memory

2.6 Interrupt

BL702/BL704/BL706 supports internal RTC wake-up and external GPIO interrupts wake-up.

The CPU interrupt controller supports a total of 64 maskable interrupt trigger sources including UART interrupt, I2C

interrupt, SPI interrupt, timer interrupt, DMA interrupt, etc. All I/O pins can be configured as external interrupt input

mode. The external interrupt supports four trigger types: high level trigger, low level trigger, rising edge trigger and

falling edge trigger.

2.7 Boot

BL702/BL704/BL706 supports multiple boot options: UART, USB, and Flash.

2.8 Power

PMU (power management unit) manages the power of the entire chip and is divided into running, idle, sleep, hiber-

nation and power off modes. The software can be configured to enter sleep mode and wake-up via RTC timer or EINT to

achieve low-power sleep and accurate wake-up management.

Power down sleep modes are flexible for applications to configure as the lowest power consumption.

2.9 Clock

Clock control unit generates clocks to the core MCU and the peripheral SOC devices. The root clock source can be

XTAL, PLL or RC oscillator. Dynamic power-saved by proper configurations such as sel, div, en, etc. PMU runs at

32KHz clock to keep system low-power in sleep mode.

BL702/704/706 Datasheet

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BL702/704/706 Datasheet(PDF) 13 Page - Bouffalo Lab Intelligent Technology Co., Ltd.