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TMS320F Datasheet(PDF) 84 Page - Texas Instruments |
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TMS320F Datasheet(HTML) 84 Page - Texas Instruments |
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84 / 389 page ![]() CPU Interrupt Registers 5-20 Figure 5–6. Interrupt Mask Register (IMR) — Address 0004h 15–6 5 4 3 2 1 0 Reserved INT6 INT5 INT4 INT3 INT2 INT1 0 R/W–x R/W–x R/W–x R/W–x R/W–x R/W–x Note: 0 = Always read as zeros, R = Read access, W = Write access, –n = Value after reset, x = value unchanged by reset Bits 15–6 Reserved. These bits are always read as 0s. Bit 5 INT6. Interrupt 6 mask. This bit masks or unmasks interrupt level INT6. 0 = Level INT6 is masked. 1 = Level INT6 is unmasked. Bit 4 INT5. Interrupt 5 mask. This bit masks or unmasks interrupt level INT5. 0 = Level INT5 is masked. 1 = Level INT5 is unmasked. Bit 3 INT4. Interrupt 4 mask. This bit masks or unmasks interrupt level INT4. 0 = Level INT4 is masked. 1 = Level INT4 is unmasked. Bit 2 INT3. Interrupt 3 mask. This bit masks or unmasks interrupt level INT3. 0 = Level INT3 is masked. 1 = Level INT3 is unmasked. Bit 1 INT2. Interrupt 2 mask. This bit masks or unmasks interrupt level INT2. 0 = Level INT2 is masked. 1 = Level INT2 is unmasked. Bit 0 INT1. Interrupt 1 mask. This bit masks or unmasks interrupt level INT1. 0 = Level INT1 is masked. 1 = Level INT1 is unmasked. |
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