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P82C150AHT Datasheet(PDF) 14 Page - NXP Semiconductors |
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P82C150AHT Datasheet(HTML) 14 Page - NXP Semiconductors |
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14 / 36 page ![]() 1996 Jun 19 14 Philips Semiconductors Preliminary specification CAN Serial Linked I/O device (SLIO) with digital and analog port functions P82C150 7.3 CAN functions The P82C150 meets the CAN protocol specification version 2.0 A and B (passive) with restricted bit timing because of the on-chip RC-oscillator and the automatic bit rate detection. In a system with P82C150 nodes there must be at least one conventional crystal-driven CAN controller (host node) which is compatible to the CAN specification V1.2 or later to control P82C150 nodes. Host nodes compatible to CAN specification V1.1 can also be used provided that the P82C150 nodes are powered by a high-accuracy power supply or they are in external oscillator mode (refer to Section 11.3). Each time a P82C150 node receives a Data Frame, it initiates the transmission of a Data Frame containing four bits status information, the register address (previously received) and the current contents of the addressed register (exception: see Section 7.3.3.1). This enables the host node to verify that the addressed register has correctly been written in case of writeable registers, and to read the contents in case of readable registers. 7.3.1 CAN IDENTIFIER Data and Remote Frames to be processed by the P82C150 are of Standard Format with 11 Identifier bits ID.10 to ID.0. Frames with extended Identifier (CAN specification version 2.0 B) are ignored. The way of identifier programming is based on two facts: • Each P82C150 operates with only two Identifiers distinguished by the LSB (see Tables 5, 6 and 7). The identifier with the higher priority is used for Data Frame reception. An extra Identifier is used for calibration purposes. • There can be maximum sixteen P82C150 circuits in one network. Table 5 Message types and format Note 1. DLC = Data Length Code; DIR = LSB of Identifier (see Section 7.3.1). Table 6 Standard Format Identifier bits ID.10 to ID.0 1 = recessive; 0 = dominant Table 7 Description of the Standard Format Identifier bits FRAME TRANSMISSION BY 82C150 RECEPTION AT 82C150 Data Frame yes (DLC = 3; DIR = 1) yes (DLC = 3; DIR = 0; calibration message with DLC = 2 to 8 allowed, see Section 7.3.10) Remote Frame no yes (DLC = 3; DIR = 1) Error Frame yes yes Overload Frame yes (only as a response) yes IDENTIFIER ID.10 ID.9 ID.8 ID.7 ID.6 ID.5 ID.4 ID.3 ID.2 ID.1 ID.0 0 1 P3 1 0 P2 P1 P0 1 0 DIR RTR BIT SYMBOL DESCRIPTION ID.8 P3 Programmable identifier bits read from Port pins P3 to P0 during reset. The input levels on P3 to P0, for example set by resistors to VSS or to VDD, are latched in the Identifier latch with the falling edge of the RST input signal. They represent the variable part of the Identifier, while the remaining bits are fixed (mask-programmed), P3 to P0 can be used as I/O ports after reset. ID.5 to ID.3 P2 to P0 ID.0 DIR DIR = 1 for transmission of Data Frames to the host. It must be set to a logic 1 in Remote Frames and to a logic 0 in Data Frames received from the host. RTR Remote Transmission Request bit. |
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