P89C738 datasheet(21/64 Pages) PHILIPS

21 / 64 page

1998 Apr 07

Philips Semiconductors

Product speciﬁcation

8-bit Flash microcontrollers

P89C738; P89C739

10.2

Timer 2

Timer 2 is functionally similar to the Timer 2 of the 8052AH. Timer 2 is a 16-bit timer/counter which is formed by two

SFRs, TL2 and TH2. Another pair of SFRs, RCAP2L and RCAP2H, form a 16-bit capture register or a 16-bit reload

Like Timer 0 and Timer 1, Timer 2 can operate either as timer or as event counter. This is selected by bit C/T2 in SFR

T2CON. The timer has three operating modes: ‘capture’, ‘autoload’ and ‘baud rate generator’, which are selected by bits

in SFR T2CON (see Tables 14 and 15).

10.2.1

TIMER/COUNTER 2CONTROL REGISTER (T2CON)

Table 14 Timer/Counter 2 Control Register (SFR address C8H)

Table 15 Description of T2CON bits

Table 16 Timer 2 operating modes

X = don’t care.

76543210

TF2

EXF2

RCLK

TCLK

EXEN2

TR2

C/T2

CP/RL2

BIT

SYMBOL

DESCRIPTION

TF2

Timer 2 overﬂow ﬂag. Set by a Timer 2 overﬂow and must be cleared by software. TF2

will not be set when either RCLK = 1 or TCLK = 1. When Timer 2 interrupt is enabled,

TF2 = 1 will cause the CPU to vector to Timer 2 interrupt routine.

EXF2

Timer 2 external ﬂag. Set when either a capture or reload is caused by a negative

transition on T2EX and when EXEN2 = 1. When Timer T2 interrupt is enabled,

EXF2 = 1 will cause the CPU to vector to Timer 2 interrupt routine.

RCLK

Receive clock ﬂag. When set, causes the Serial Port to use Timer 2 overﬂow pulses

for its receive clock in Modes 1 and 3. RCLK = 0 causes Timer 1 overﬂows to be used

for the receive clock.

TCLK

Transmit clock ﬂag. When set, causes the Serial Port to use Timer 2 overﬂow pulses

for its transmit clock in Modes 1 and 3. TCLK = 0 causes Timer 1 overﬂows to be used

for the transmit clock.

EXEN2

Timer 2 external enable ﬂag. When set, allows a capture or reload to occur as a result

of a negative transition on T2EX, if Timer 2 is not being used to clock the Serial Port.

EXEN2 = 0, causes Timer 2 to ignore events at T2EX.

TR2

Timer 2 start/stop control. TR2 = 1 starts Timer 2; TR2 = 0 stops Timer 2.

1C/T2

Timer 2 timer or counter select. C/T2 = 0 selects the internal timer with a clock

frequency of 1

⁄12fclk. C/T2 = 1 selects the external event counter; falling edge triggered.

CP/RL2

Capture/reload ﬂag. When set, capture will occur on negative transitions at T2EX if

EXEN2 = 1. When cleared, reloads will occur upon either Timer 2 overﬂows or negative

transitions at T2EX if EXEN2 = 1. When either RCLK = 1 or TCLK = 1, this bit is ignored

and the timer is forced to reload upon overﬂow.

RCLK

TCLK

CP/RL2

TR2

MODE

0001

16-bit automatic reload

0011

16-bit capture

baud rate generator

off

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