NXP Semiconductors

PCF85063A

Tiny Real-Time Clock/calendar with alarm function and I2C-bus

– If TF is not cleared before the next coming interrupt, no INT is generated

– the countdown timer stops after the first countdown

7.2.2.4 COF[2:0]: Clock output frequency

A programmable square wave is available at pin CLKOUT. Operation is controlled by the COF[2:0] bits in the

register Control_2. Frequencies of 32.768 kHz (default) down to 1 Hz can be generated for use as a system

clock, microcontroller clock, input to a charge pump, or for calibration of the oscillator.

Pin CLKOUT is a push-pull output and enabled at power-on. CLKOUT can be disabled by setting COF[2:0] to

111 or by setting CLKOE LOW (PCF85063ATL only). When disabled, the CLKOUT is LOW. If CLKOE is HIGH

and COF[2:0]=111 there will be no clock and CLKOUT will be LOW.

The duty cycle of the selected clock is not controlled. However, due to the nature of the clock generation, all

clock frequencies except 32.768 kHz have a duty cycle of 50 : 50.

The STOP bit function can also affect the CLKOUT signal, depending on the selected frequency. When the

STOP bit is set logic 1, the CLKOUT pin generates a continuous LOW for those frequencies that can be

stopped. For more details of the STOP bit function, see Section 7.2.1.2.

COF[2:0]

CLKOUT frequency (Hz)

Typical duty cycle[1]

Effect of STOP bit

000[2]

32 768

60 : 40 to 40 : 60

no effect

001

16 384

50 : 50

no effect

010

8 192

50 : 50

no effect

011

4 096

50 : 50

CLKOUT = LOW

100

2 048

50 : 50

CLKOUT = LOW

101

1 024

50 : 50

CLKOUT = LOW

110

1[3]

50 : 50

CLKOUT = LOW

111

CLKOUT = LOW

-

-

Table 10. CLKOUT frequency selection

[1]

Duty cycle definition: % HIGH-level time : % LOW-level time.

[2]

Default values: The duty cycle of the CLKOUT when outputting 32,768 Hz could change from 60:40 to 40:60 depending on the detector since the 32,768

Hz is derived from the oscillator output which is not perfect. It could change from device to device and it depends on the silicon diffusion. There is nothing

that can be done from outside the chip to influence the duty cycle.

[3]

1 Hz clock pulses are affected by offset correction pulses.

7.2.3 Register Offset

The PCF85063A incorporates an offset register (address 02h) which can be used to implement several

functions, such as:

• Accuracy tuning

• Aging adjustment

• Temperature compensation

Bit

Symbol

Value

Description

offset mode

0[1]

normal mode: offset is made once every two hours

7

MODE

1

course mode: offset is made every 4 minutes

Table 11. Offset - offset register (address 02h) bit description

PCF85063A

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Product data sheet

Rev. 7.1 — 8 November 2023

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