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ADC3908CSSS Datasheet(PDF) 4 Page - Texas Instruments |
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ADC3908CSSS Datasheet(HTML) 4 Page - Texas Instruments |
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4 / 131 page  Table 4-1. Pin Functions (continued) PIN TYPE DESCRIPTION NAME NO. D0 4 O CMOS digital lane output data. D1 3 O D2 2 O D3 1 O D4 32 O D5 31 O D6 26 O D7 25 O D8 24 O D9 23 O D10 22 O D11 21 O DCLK 30 O CMOS output for data bit clock. DCLK/FCLK 29 O Default is Inverse data bit clock for CMOS output data. Frame clock can be selected via SPI write DCLKIN 5 I Data input clock for serial CMOS interface. OEN/PD 6 I Output data enable. This pin is active low with default 60 kΩ pull-down. Can be configured as power down pin through SPI. POWER SUPPLY AVDD 12, 13 I Analog 1.8 V power supply GND PowerPAD™ I Analog Ground, 0 V IOVDD 27 I 1.8 V to 3.3 V power supply for digital interface DGND 28 I Ground, 0 V for digital interface ADC3910D125 SBASAD1 – DECEMBER 2023 www.ti.com 4 Submit Document Feedback Copyright © 2023 Texas Instruments Incorporated Product Folder Links: ADC3910D125 |
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