W39V080FAQZ datasheet(25/35 Pages) WINBOND

25 / 35 page

W39V080FA

Publication Release Date: Dec. 13, 2005

- 25 -

Revision A5

10. FWH INTERFACE MODE AC CHARACTERISTICS

10.1 AC Test Conditions

PARAMETER

CONDITIONS

Input Pulse Levels

0.6 VDD to 0.2 VDD

Input Rise/Fall Slew Rate

1 V/nS

Input/Output Timing Level

0.4VDD / 0.4VDD

Output Load

1 TTL Gate and CL = 10 pF

10.2 Read/Write Cycle Timing Parameters

(VDD = 3.3V

± 0.3V, VSS = 0V, TA = 0 to 70° C)

W39V080FA

PARAMETER

SYMBOL

MIN.

MAX.

UNIT

Clock Cycle Time

TCYC

Input Set Up Time

TSU

Input Hold Time

THD

Clock to Data Valid

TKQ

Note: Minimum and Maximum time have different load. Please refer to PCI specification.

10.3 Reset Timing Parameters

PARAMETER

SYMBOL

MIN.

TYP.

MAX.

UNIT

VDD stable to Reset Active

TPRST

Clock Stable to Reset Active

TKRST

100

μS

Reset Pulse Width

TRSTP

100

Reset Active to Output Float

TRSTF

Reset Inactive to Input Active

TRST

μS

Note: All AC timing signals observe the following guidelines for determining setup and hold times:

(a) High level signal's reference level is input high and

(b) low level signal's reference level is input low.

Please refer to the AC testing condition.

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