Electronic Components Datasheet Search
  British  ▼
ALLDATASHEET.CO.UK

X  

PCF2105MU/2 Datasheet(PDF) 20 Page - NXP Semiconductors

Part # PCF2105MU/2
Description  LCD controller/driver
PDF  48 Pages
Scroll/Zoom Zoom In 100%  Zoom Out
Manufacturer  PHILIPS [NXP Semiconductors]
Direct Link  http://www.nxp.com
Logo PHILIPS - NXP Semiconductors

PCF2105MU/2 Datasheet(HTML) 20 Page - NXP Semiconductors

Back Button PCF2105MU/2 Datasheet HTML 16Page - NXP Semiconductors PCF2105MU/2 Datasheet HTML 17Page - NXP Semiconductors PCF2105MU/2 Datasheet HTML 18Page - NXP Semiconductors PCF2105MU/2 Datasheet HTML 19Page - NXP Semiconductors PCF2105MU/2 Datasheet HTML 20Page - NXP Semiconductors PCF2105MU/2 Datasheet HTML 21Page - NXP Semiconductors PCF2105MU/2 Datasheet HTML 22Page - NXP Semiconductors PCF2105MU/2 Datasheet HTML 23Page - NXP Semiconductors PCF2105MU/2 Datasheet HTML 24Page - NXP Semiconductors Next Button
Zoom Inzoom in Zoom Outzoom out
 20 / 48 page
background image
1998 Jul 30
20
Philips Semiconductors
Product specification
LCD controller/driver
PCF2105
10 INTERFACE TO MICROCONTROLLER
(PARALLEL INTERFACE)
The PCF2105 can send data in either two 4-bit modes or
one 8-bit mode and can thus interface to 4 or 8-bit
microcontrollers.
In the 8-bit mode data is transferred as 8-bit bytes using
the 8 data lines DB7 to DB0. The control lines E, RS,
and R/W are required.
In the 4-bit mode data is transferred in two cycles of 4-bits
each. The higher order bits (corresponding to DB7 to DB4
in 8-bit mode) are sent in the first cycle and the lower order
bits (DB3 to DB0 in 8-bit mode) in the second cycle. Data
transfer is complete after two 4-bit data transfers. It should
be noted that two cycles are also required for the busy flag
check. The 4-bit mode is selected by instruction.
See Figs 13, 14 and 15 for examples of bus protocol.
In the 4-bit mode, the pads DB3 to DB0 must be left
open-circuit. They are pulled up to VDD internally.
Fig.13 4-bit transfer example.
MGA804
RS
E
DB7
R/W
DB6
DB5
DB4
instruction
write
busy flag and
address counter read
data register
read
IR7
IR3
BF
AC3
DR7
DR3
IR6
IR2
AC6
AC2
DR6
DR2
IR5
IR1
AC5
AC1
DR5
DR1
IR4
IR0
AC4
AC0
DR4
DR0



Html Pages

1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 33 34 35 36 37 38 39 40 41 42 43 44 45 46 47 48


Datasheet Download

Go To PDF Page


Link URL



Does ALLDATASHEET help your business so far?  [ DONATE ] 

About Alldatasheet   |   Advertisement   |   Contact us   |   Privacy Policy   |   Link to Datasheet    |   Link Exchange   |   Manufacturer List
All Rights Reserved©Alldatasheet.com


Mirror Sites
English : Alldatasheet.com  |   English : Alldatasheet.net  |   Chinese : Alldatasheetcn.com  |   German : Alldatasheetde.com  |   Japanese : Alldatasheet.jp
Russian : Alldatasheetru.com  |   Korean : Alldatasheet.co.kr  |   Spanish : Alldatasheet.es  |   French : Alldatasheet.fr  |   Italian : Alldatasheetit.com
Portuguese : Alldatasheetpt.com  |   Polish : Alldatasheet.pl  |   Vietnamese : Alldatasheet.vn
Indian : Alldatasheet.in  |   Mexican : Alldatasheet.com.mx  |   British : Alldatasheet.co.uk  |   New Zealand : Alldatasheet.co.nz
Family Site : ic2ic.com  |   icmetro.com