Philips Semiconductors

Product specification

PCK2001R

2000 Jul 25

5

AC CHARACTERISTICS

SYMBOL

PARAMETER

TEST CONDITIONS

LIMITS

UNIT

NOTES

MIN

MAX

CLK period

1, 6

29.9

30.0

30.2

CLK HIGH time

33MHz

2, 6, 8

12.3

14.3

16.3

ns

CLK LOW time

3, 6, 8

12.1

14.1

16.1

CLK period

1, 6

14.9

15.0

15.2

CLK HIGH time

66MHz

2, 6, 8

5.6

6.8

8.0

ns

CLK LOW time

3, 6, 8

5.3

6.5

7.7

CLK period

1,6

9.9

10.01

10.2

CLK HIGH time

100MHz

2, 6, 8

3.3

4.2

5.1

ns

CLK LOW time

3, 6, 8

3.2

4.1

5.0

CLK period

1, 6

7.4

7.5

7.7

CLK HIGH time

133MHz

2, 6, 8

2.6

3.1

3.6

ns

CLK LOW time

3, 6, 8

2.2

2.7

3.2

Rise time

4, 6, 10

1.5

2.0

4.0

V/ns

Fall time

4, 6, 11

1.5

2.5

4.0

V/ns

Buffer LH propagation delay

6, 7

1.0

2.4

3.5

ns

Buffer HL propagation delay

6, 7

1.0

2.6

3.5

ns

DUTY CYCLE

Output Duty Cycle

Measured at 1.5V

5, 6, 7

45

50

55

%

Bus CLK skew

1, 6

150

250

ps

Device to device skew

500

ps

NOTES:

1. Clock period and skew are measured on the rising edge at 1.5V.

5. Duty cycle should be tested with a 50/50% input.

6. Over MIN (20pF) to MAX (30pF) discrete load, process, voltage, and temperature.

7. Input edge rate for these tests must be faster than 1 V/ns.

8. Calculated at minimum edge rate (1.5ns) to guarantee 45/55% duty cycle at 1.5V. Pulsewidth is required to be wider at the faster edge to

ensure duty cycle specification is met.

10. Typical is measured with MAX (30pF) discrete load.

11. Typical is measured with MIN (20pF) discrete load.