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PCK2014ADL Datasheet(PDF) 2 Page - NXP Semiconductors |
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PCK2014ADL Datasheet(HTML) 2 Page - NXP Semiconductors |
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2 / 16 page  Philips Semiconductors Product specification PCK2014A CK98 (100/133 MHz) spread spectrum system clock generator 2 2001 Apr 02 853–2245 25964 FEATURES • ESD classification testing is done to JEDEC Standard JESD22. Protection exceeds 2000 V to HBM per method A114. • Latch-up testing is done to JEDEC Standard JESD78 which exceeds 100 mA. • Mixed 2.5 V and 3.3 V operation • Six CPU clocks at 2.5 V • Six PCI clocks at 3.3 V, one free-running (synchronous with CPU clocks) • Two 3.3 V fixed clocks @ 66 MHz • Three 2.5 V IOAPIC clocks @ 16.67 MHz • One 3.3 V 48 MHz USB clock • Two 3.3 V reference clocks @ 14.318 MHz • Reference 14.31818 MHz Xtal oscillator input • 133 MHz or 100 MHz operation • Power management control input pins • CPU clock jitter ≤ 150 ps cycle-cycle • CPU clock skew ≤ 175 ps pin-pin • 0.0 ns – 1.5 ns CPU - 3V66 delay • 1.5 ns – 3.5 ns 3V66 - PCI delay • 1.5 ns – 4.0 ns CPU - IOAPIC delay • 1.5 ns – 4.0 ns CPU - PCI delay • Available in 56-pin SSOP package • ±0.6% Center spread spectrum capability via select pins • –0.6% Down spread spectrum capability via select pins DESCRIPTION The PCK2014A is a clock generator (frequency synthesizer) chip for a Pentium III and other similar processors. The PCK2014A has six CPU clock outputs at 2.5 V, two 3V66 clocks running at 66 MHz. there are six PCI clock outputs running at 33 MHz. Additionally, the part has three 2.5 V IOAPIC clock outputs at 16.67 MHz and two 3.3 V reference clock outputs at 14.318 MHz. All clock outputs meet Intel’s drive strength, rise/fall time, jitter, accuracy, and skew requirements. The part possesses dedicated power-down, CPUSTOP, and PCISTOP input pins for power management control. These inputs are synchronized on-chip and ensure glitch-free output transitions. When the CPUSTOP input is asserted, the CPU clock outputs and 3V66 clock outputs are driven LOW. When the PCISTOP input is asserted, the PCI clock outputs are driven LOW. Finally, when the PWRDWN input pin is asserted, the internal reference oscillator and PLLs are shut down, and all outputs are driven LOW. PIN CONFIGURATION SW00879 1 2 3 4 5 6 7 8 9 10 11 12 45 46 47 48 49 50 51 52 53 54 55 56 VSS REF1 VDD3V XTAL_IN XTAL_OUT VSS VSS PCI_F VDD3V PCI_1 CPUCLK0 VSS CPUCLK1 VDD3V CPUCLK2 PCI_2 13 14 15 16 17 18 39 40 41 42 43 44 VSS PCI_3 PCI_4 VDD3V VDD3V CPUCLK3 PCI_5 19 38 VSS 20 21 22 23 24 25 32 33 34 35 36 37 VDD3V VSS VDD3V SEL1 SEL0 VSS 26 31 27 30 48MHz_USB 28 29 SEL133/100 REF0 VSS 3V66_0 3V66_1 VDD3V VDD25V APIC2 APIC1 APIC0 VDD25V CPUCLK5 CPUCLK4 VSS VDD25V VSS VDD25V VSS VSS PCISTOP CPUSTOP PWRDWN SPREAD VDD3V VSS ORDERING INFORMATION PACKAGES TEMPERATURE RANGE ORDER CODE DRAWING NUMBER 56-pin plastic SSOP 0 to +70 °C PCK2014ADL SOT371-1 Intel and Pentium are registered trademarks of Intel Corporation. |
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