Philips Semiconductors

Product specification

PCK953

50–125 MHz PECL input/CMOS output

3.3 V PLL clock driver

2001 Feb 08

5

APPLICATION INFORMATION

Power supply filtering

The PCK953 is a mixed analog/digital product and as such it

exhibits some sensitivities that would not necessarily be seen on a

fully digital product. Analog circuitry is naturally susceptible to

random noise, especially if this noise is seen on the power supply

pins. The PCK953 provides separate power supplies for the output

purpose of this design technique is to try to isolate the high

switching noise digital outputs from the relatively sensitive internal

analog phase-locked loop. In a controlled environment such as an

evaluation board, this level of isolation is sufficient. However, in a

digital system environment where it is more difficult to minimize

noise on the power supplies, a second level of isolation may be

required. The simplest form of isolation is a power supply filter on

Figure 1 illustrates a typical power supply filter scheme. The

PCK953 is most susceptible to noise with spectral content in the

1 kHz to 1 MHz range. Therefore, the filter should be designed to

target this range. The key parameter that needs to be met in the

final filter design is the DC voltage drop that will be seen between

pin) is typically 15 mA (20 mA maximum), assuming that a minimum

shown in Figure 1 must have a resistance of 10–15

Ω to meet the

voltage drop criteria. The RC filter pictured will provide a broadband

filter with approximately 100:1 attenuation for noise whose spectral

content is above 20 kHz. As the noise frequency crosses the series

resonant point of an individual capacitor, its overall impedance

begins to look inductive, and thus increases with increasing

frequency. The parallel capacitor combination shown ensures that a

low impedance path to ground exists for frequencies well above the

bandwidth of the PLL. It is recommended that the user start with an

8–10

move to the higher value resistors when a higher level of attenuation

is shown to be needed.

PCK953

0.01

µF

3.3 V

0.01

µF

22

µF

SW00626

Figure 1. Power supply filter

Although the PCK953 has several design features to minimize the

susceptibility to power supply noise (isolated power and grounds

and fully differential PLL) there still may be applications in which

overall performance is being degraded due to system power supply

noise. The power supply filter schemes discussed in this section

should be adequate to eliminate power supply noise related

problems in most designs.

Driving transmission lines

The PCK953 clock driver was designed to drive high speed signals

in a terminated transmission line environment. To provide the

optimum flexibility to the user, the output drivers were designed to

exhibit the lowest impedance possible. With an output impedance of

less than 20

Ω, the drivers can drive either parallel or series

terminated transmission lines.

In most high performance clock networks, point-to-point distribution

of signals is the method of choice. In a point-to-point scheme either

series terminated or parallel terminated transmission lines can be

used. The parallel technique terminates the signal at the end of the

line with a 50

high level of DC current, and thus only a single terminated line can

be driven by each output of the PCK953 clock driver. For the series

terminated case, however, there is no DC current draw, thus the

outputs can drive multiple series terminated lines. Figure 2 illustrates

an output driving a single series terminated line versus two series

terminated lines in parallel. When taken to its extreme, the fanout of

the PCK953 clock driver is effectively doubled due to its capability to

drive multiple lines.

PCK953

SW00627

14

Ω

OUTPUT

BUFFER

IN

OutA

PCK953

14

Ω

OUTPUT

BUFFER

IN

OutB1

OutB0

Figure 2. Single versus dual transmission lines

The waveform plots of Figure 3 show the simulation results of an

output driving a single line versus two lines. In both cases, the drive

capability of the PCK953 output buffers is more than sufficient to

drive 50

Ω transmission lines on the incident edge. Note from the

delay measurements in the simulations, a delta of only 43 ps exists

between the two differently loaded outputs. This suggests that the

dual line driving need not be used exclusively to maintain the tight

output-to-output skew of the PCK953. The output waveform in

Figure 3 shows a step in the waveform; this step is caused by the

impedance mismatch seen looking into the driver. The parallel

combination of the 43

Ω series resistor plus the output impedance

does not match the parallel combination of the line impedances. The

voltage wave launched down the two lines will equal:

VL = 3.0 (25 / (18 + 14 + 25) = 3.0 (25 / 57) = 1.31 V