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TSL25213 Datasheet(PDF) 48 Page - OSRAM GmbH |
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TSL25213 Datasheet(HTML) 48 Page - OSRAM GmbH |
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48 / 81 page  Datasheet, Public Page 47 [v3-00] 2022-Dec-21 Document Feedback TSL2521 − Register Overview MEAS_SEQR_RESIDUAL_1_AND_WAIT Register Figure 60: MEAS_SEQR_RESIDUAL_1_AND_WAIT Note(s): 1. Return to the Register Map (0xD3). Addr: 0xD3 MEAS_SEQR_RESIDUAL_1_AND_WAIT Bit Field Reset Type Bit Description 7:4 MEASUREMENT_ SEQUENCER_ WAIT_PATTERN 0x1 R/W Defines if a sequencer step will wait for the modulator trigger timer to finish as programmed in MOD_TRIGGER_TIMING and WTIME. At the same time the timer is restarted. In case this bit is not set, the next sequencer step will start as soon as all measurements in the prior step are completed. Please observe that MOD_TRIGGER_TIMING is “0” by default. In this case the programmed wait pattern is ignored since measurement time has always priority over wait time. The bit pattern does not represent a value but controls bitwise which sequencer step shall be used. The leftmost position of “0000” refers to sequencer step 3, the rightmost refers to sequencer step 0. By default the wait is executed for sequencer step 0 (last sequencer step). 3:0 Reserved 0xF R/W |
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