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MPC8313E Datasheet(PDF) 13 Page - Freescale Semiconductor, Inc |
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MPC8313E Datasheet(HTML) 13 Page - Freescale Semiconductor, Inc |
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13 / 88 page ![]() MPC8313E PowerQUICC™ II Pro Processor Hardware Specifications, Rev. 0 Freescale Semiconductor 13 Clock Input Timing 4 Clock Input Timing This section provides the clock input DC and AC electrical characteristics for the MPC8313E. 4.1 DC Electrical Characteristics Table 6 provides the clock input (SYS_CLK_IN/PCI_SYNC_IN) DC timing specifications for the MPC8313E. 4.2 AC Electrical Characteristics The primary clock source for the MPC8313E can be one of two inputs, SYS_CLK_IN or PCI_CLK, depending on whether the device is configured in PCI host or PCI agent mode. Table 7 provides the clock input (SYS_CLK_IN/PCI_CLK) AC timing specifications for the MPC8313E. Table 6. SYS_CLK_IN DC Electrical Characteristics Parameter Condition Symbol Min Max Unit Input high voltage — VIH 2.7 NVDD +0.3 V Input low voltage — VIL –0.3 0.4 V SYS_CLK_IN Input current 0 V ≤ VIN ≤ NVDD IIN —±10 μA PCI_SYNC_IN Input current 0 V ≤ VIN ≤ 0.5 V or NVDD – 0.5 V ≤ VIN ≤ NVDD IIN —±10 μA PCI_SYNC_IN Input current 0.5 V ≤ VIN ≤ NVDD – 0.5 V IIN —±50 μA Table 7. SYS_CLK_IN AC Timing Specifications Parameter/Condition Symbol Min Typical Max Unit Notes SYS_CLK_IN/PCI_CLK frequency fSYS_CLK_IN 25 — 66 MHz 1 SYS_CLK_IN/PCI_CLK cycle time tSYS_CLK_IN 15 — — ns — SYS_CLK_IN/PCI_CLK rise and fall time tKH, tKL 0.6 0.8 1.2 ns 2 SYS_CLK_IN/PCI_CLK duty cycle tKHK/tSYS_CLK_IN 40 — 60 % 3 SYS_CLK_IN/PCI_CLK jitter — — — ±150 ps 4, 5 Notes: 1. Caution: The system, core, security block must not exceed their respective maximum or minimum operating frequencies. 2. Rise and fall times for SYS_CLK_IN/PCI_CLK are measured at 0.4 V and 2.7 V. 3. Timing is guaranteed by design and characterization. 4. This represents the total input jitter—short term and long term—and is guaranteed by design. 5. The SYS_CLK_IN/PCI_CLK driver’s closed loop jitter bandwidth should be < 500 kHz at –20 dB. The bandwidth must be set low to allow cascade-connected PLL-based devices to track SYS_CLK_IN drivers with the specified jitter. |
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