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ADAR5001ACBZ-R7 Datasheet(PDF) 1 Page - Analog Devices |
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ADAR5001ACBZ-R7 Datasheet(HTML) 1 Page - Analog Devices |
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1 / 9 page ![]() Data Sheet ADAR5001 10 GHz to 40 GHz, 2-Way RF Splitter Combiner Rev. 0 DOCUMENT FEEDBACK TECHNICAL SUPPORT Information furnished by Analog Devices is believed to be accurate and reliable "as is". However, no responsibility is assumed by Analog Devices for its use, nor for any infringements of patents or other rights of third parties that may result from its use. Specifications subject to change without notice. No license is granted by implication or otherwise under any patent or patent rights of Analog Devices. Trademarks and registered trademarks are the property of their respective owners. FEATURES ► 2-way RF splitter combiner ► Frequency range: 10 GHz to 40 GHz ► Insertion loss (excess of 3 dB): ► −1 dB from 10 GHz to 18 GHz ► −1.1 dB from 18 GHz to 27 GHz ► Return loss (Port S1): ► −15 dB from 10 GHz to 18 GHz ► −12 dB from 18 GHz to 27 GHz ► Isolation: ► −20 dB at 10 GHz to 18 GHz ► −23 dB from 18 GHz to 27 GHz ► 1.460 mm × 1.460 mm × 0.500 mm, wafer level chip-scale package (WLCSP) APPLICATIONS ► General-purpose microwave signal distribution ► Phased-array satellite communication (SATCOM) systems ► Phased-array radar systems GENERAL DESCRIPTION The ADAR5001 is a 1-to-2 Wilkinson power splitter that is designed for space-constrained microwave signal distribution applications. Excess insertion loss ranges from −1.0 dB (from 10 GHz to 18 GHz) and −1.1 dB (from 18 GHz to 27 GHz). The two outputs are matched in both phase and amplitude, making the ADAR5001 ideal for signal distribution applications requiring low time skew between channels. The ADAR5001 can also be used as a combiner, combin- ing input signals at the P1 and P2 ports to an output at the S1 port. The ADAR5001 is housed in a compact, 1.460 mm × 1.460 mm × 0.500 mm WLCSP, which makes it ideal for use in planar, phased-array antenna systems that require a tight pitch between elements. The ADAR5001 is fabricated on a passive silicon process, and it is specified to operate from −40°C to +85°C. FUNCTIONAL BLOCK DIAGRAM Figure 1. Functional Block Diagram |
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