PLS101 datasheet(5/8 Pages) PHILIPS

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INPUT

F0 – F7

1.5V

tPD

tCE

tCD

VOL

VOH

+3.0V

Read Cycle

Philips Semiconductors Programmable Logic Devices

Product specification

PLS100/PLS101

Programmable logic arrays

(16

× 48 × 8)

October 22, 1993

AC ELECTRICAL CHARACTERISTICS

°C < Tamb < +75°C, 4.75 < VCC < 5.25V, R1 = 470Ω, R2 = 1kΩ

LIMITS

SYMBOL

PARAMETER

FROM

MIN

TYP1

MAX

UNIT

Propagation delay2

tPD

Input

Output

Input

tCE

Chip Enable3

Output

Chip Enable

Disable time

tCD

Chip Disable3

Output

Chip Enable

NOTES:

1. All typical values are at VCC = 5V. Tamb = +25°C.

2. All propagation delays are measured and specified under worst case conditions.

3. For 3-State output; output enable times are tested with CL = 30pF to the 1.5V level, and S1 is open for high-impedance to High tests and

closed for high-impedance to Low tests. Output disable times are tested with CL = 5pF. High-to-High impedance tests are made to an output

voltage of VT = (VOH – 0.5V) with S1 open, and Low-to-High impedance tests are made to the VT = (VOL + 0.5V) level with S1 closed.

VOLTAGE WAVEFORMS

TEST LOAD CIRCUIT

MEASUREMENTS:

All circuit delays are measured at the +1.5V level of in-

puts and outputs, unless otherwise specified.

90%

10%

5ns

90%

10%

+3.0V

Input Pulses

+5V

GND

INPUTS

I15

OUTPUTS

DUT

NOTE:

C1 and C2 are to bypass VCC to GND.

VCC

TIMING DEFINITIONS

SYMBOL

PARAMETER

tCE

Delay between beginning of

Chip Enable Low (with Input

valid) and when Data Output

becomes valid.

tCD

Delay between when Chip

Enable becomes High and

Data Output is in off state

(Hi-Z or High).

tPD

Delay between beginning of

valid Input (with Chip Enable

Low) and when Data Output

becomes valid.

TIMING DIAGRAM

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