MPC866 datasheet(71/96 Pages) FREESCALE

71 / 96 page

MPC866/MPC859 Hardware Specifications, Rev. 2

Freescale Semiconductor

CPM Electrical Characteristics

Table 28 shows the I2C (SCL < 100 kHz) timings.

Table 29 shows the I2C (SCL > 100 kHz) timings.

Table 28. I2C Timing (SCL < 100 kHz)

Num

Characteristic

All Frequencies

Unit

Min

Max

200

SCL clock frequency (slave)

100

kHz

200

SCL clock frequency (master) 1

SCL frequency is given by SCL = BRGCLK_frequency / ((BRG register + 3) * pre_scaler * 2).

The ratio SyncClk/(BRGCLK/pre_scaler) must be greater or equal to 4/1.

1.5

100

kHz

202

Bus free time between transmissions

4.7

—

μs

203

Low period of SCL

4.7

—

μs

204

High period of SCL

4.0

—

μs

205

Start condition setup time

4.7

—

μs

206

Start condition hold time

4.0

—

μs

207

Data hold time

—

μs

208

Data setup time

250

—

209

SDL/SCL rise time

—

μs

210

SDL/SCL fall time

—

300

211

Stop condition setup time

4.7

—

μs

Table 29. I2C Timing (SCL > 100 kHz)

Num

Characteristic

Expression

All Frequencies

Unit

Min

Max

200

SCL clock frequency (slave)

fSCL

BRGCLK/48

200

SCL clock frequency (master) 1

SCL frequency is given by SCL = BrgClk_frequency / ((BRG register + 3) * pre_scaler * 2).

The ratio SyncClk/(Brg_Clk/pre_scaler) must be greater or equal to 4/1.

fSCL

BRGCLK/16512

BRGCLK/48

202

Bus free time between transmissions

—

1/(2.2 * fSCL)

—

203

Low period of SCL

—

1/(2.2 * fSCL)

—

204

High period of SCL

—

1/(2.2 * fSCL)

—

205

Start condition setup time

—

1/(2.2 * fSCL)

—

206

Start condition hold time

—

1/(2.2 * fSCL)

—

207

Data hold time

—

208

Data setup time

—

1/(40 * fSCL)

—

209

SDL/SCL rise time

—

1/(10 * fSCL)

210

SDL/SCL fall time

—

1/(33 * fSCL)

211

Stop condition setup time

—

1/2(2.2 * fSCL)

—

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