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SP7662 Datasheet(PDF) 6 Page - Sipex Corporation |
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SP7662 Datasheet(HTML) 6 Page - Sipex Corporation |
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6 / 19 page  6 Mar -07 Rev AJ SP7662 Wide Input Voltage Range 2A, 300kHz Buck Regulator © 2007 Sipex Corporation THEORY OF OPERATION General Overview The SP7662 is a fixed frequency, volt- age mode, synchronous PWM regulator optimizedforhighefficiency.Theparthas beenspecificallydesignedforsinglesupply operation from a 5V to 22V input. The heart of the SP7662 is a wide bandwidth transconductanceamplifierdesignedtoac- commodate Type II and Type III compensa- tion schemes. A precision 0.8V reference, present on the positive terminal of the error amplifier, permits the programming of the output voltage down to 0.8V via the VFB pin.Theoutputoftheerroramplifier,COMP, is compared to a .V peak-to-peak ramp, which is responsible for trailing edge PWM control. This voltage ramp and PWM control logic are governed by the internal oscillator that accurately sets the PWM frequency to 300kHz. The SP7662 contains two unique control features that are very powerful in distributed applications. First, nonsynchronous driver control is enabled during startup, to prohibit the low side switch from pulling down the output until the high side switch has at- tempted to turn on. Second, a 00% duty cycletimeoutensuresthatthe lowsideswitch is periodically enhanced during extended periods at 00% duty cycle. This guaran- tees the synchronized refreshing of the BST capacitor during very large duty ratios. The SP7662 also contains a number of valu- able protection features. Programmable VIN UVLO allows the user to set the exact value at which the conversion voltage can safely begin down-conversion, and an internal VCC UVLO which ensures that the controller itself has enough voltage to properly operate. Other protection features include thermal shutdown and short-circuit detection. In the event that either a thermal, short-circuit, or UVLO fault is detected, the SP7662 is forced into an idle state where the output drivers areheldoffforafiniteperiodbeforearestart is attempted. Soft Start “Soft Start” is achieved when a power con- verter ramps up the output voltage while controlling the magnitude of the input sup- ply source current. In a modern step down converter, ramping up the positive terminal oftheerroramplifiercontrolssoftstart.Asa result,excesssourcecurrentcanbedefined as the current required to charge the output capacitor. IViN = COut • (∆VOut / ∆TSOft-StArt) The SP7662 provides the user with the op- tion to program the soft start rate by tying acapacitorfromtheSSpintoGND.The selection of this capacitor is based on the 0µA pull up current present at the SS pin and the 0.8V reference voltage. Therefore, theexcesssourcecanberedefinedas: IViN = COut • [∆VOut •0µA / (CSS • 0.8V)] Under Voltage Lock Out (UVLO) The SP7662 has two separate UVLO com- parators to monitor the bias (Vcc) and Input (ViN)voltagesindependently.TheVccUVLO is internally set to 4.25V. The ViN UVLO is programmable through UViN pin. When UVIN pin is greater than 2.5V the SP7662 is permitted to start up pending the removal of all other faults. A pair of internal resistors isconnectedtoUVINasshowninthefigure below. SP7662 R6 R7 + - 140KΩ 50KΩ 2.5V ON 2.2V OFF GND UVIN VIN Internal and external bias of UVIN |
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