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ADN8102

Rev. C | Page 17 of 36

RECEIVERS

Input Structure and Input Levels

The ADN8102 receiver inputs incorporate 50 Ω termination

resistors, ESD protection, and a multizero transfer function

equalizer that can be optimized for backplane or cable operation.

Each channel also provides a programmable LOS function that

provides an interrupt that can be used to squelch or disable the

associated output when the differential input voltage falls below the

programmed threshold value. Each receive channel also provides a

P/N inversion function that allows the user to swap the sign of

the input signal path to eliminate the need for board-level

crossovers in the receiver channel.

Table 6 illustrates some, but not all, possible combinations of

input supply voltages.

Table 6. Common Input Voltage Levels

Configuration

VCC (V)

VTTI (V)

Low VTTI, ac-coupled input

1.8

1.6

Single 1.8 V supply

1.8

3.3 V core

3.3

1.8

Single 3.3 V supply

3.3

VCC

VTTI

VEE

SIMPLIFIED RECEIVER INPUT CIRCUIT

RLN

RLP

1kΩ

750Ω

52Ω

Figure 39. Simplified Input Structure

EQUALIZATION SETTINGS

The ADN8102 receiver incorporates a multizero transfer function,

continuous time equalizer that provides up to 22 dB of high

frequency boost at 1.875 GHz to compensate up to 30 meters

of CX4 cable or 40 inches of FR4 at 3.75 Gbps. The ADN8102

allows joint control of the equalizer transfer function of the

four equalizer channels in a single port through the I2C control

interface. Port A and Port B equalizer transfer functions are

controlled via Register 0x80 and Register 0xA0, respectively.

The equalizer transfer function allows independent control of

the boost in two different frequency ranges for optimal matching

with the loss shape of the user’s channel (for example, skin-effect

loss dominated or dielectric loss dominated). By default, the

equalizer control is simplified to two independent look up

tables (LUT) of basic settings that provide nine settings, each

optimized for CX4 cable and FR4 to ease programming for

typical channels. The default state of the part selects the CX4

optimized equalization map for the IN_A[3:0] channels that

interface with the cable and the FR4 optimized equalization map

for the IN_B[3:0] channels that interface with the board. Full

control of the equalizer is available via the I2C control interface by

writing MODE[0] = 1 at Address 0x0F. Table 8 summarizes the

high frequency boost for each of the basic control settings and

the typical length of CX4 cable and FR4 trace that each setting

compensates. Setting the EQBY bit of the IN_A/IN_B configuration

registers high sets the equalization to 1.5 dB of boost, which

compensates 0 meters to 2 meters of CX4 or 0 inches to

5 inches of FR4.

Setting the LUT SELECT bit = 1 (Bit 1 in the IN_Ax/IN_Bx FR4

control registers) allows the default map selection (CX4 or FR4

optimized) to be overwritten via the LUT FR4/CX4 bit (Bit 0)

in the IN_Ax/IN_Bx FR4 control registers. Setting this bit high

selects the FR4 optimized map, and setting it low selects the CX4

optimized map. These settings are set on a per channel basis

(see Table 9 and Table 22).

Table 7.

LUT SELECT

LUT FR4/CX4

Description

0 (default)

Port A eq optimized for CX4

cable

Port B eq optimized for FR4

PCB trace

Eq optimized for CX4 cable

Eq optimized for FR4 PCB trace

X = don’t care.

Advanced Equalization Settings

The user can also specify the boost in the midfrequency and high

frequency ranges independently. This is done by writing to the

IN_A/IN_B EQ1 control and IN_A/IN_B EQ2 control registers for

the channel of interest. Each of these registers provides 32 settings

of boost, with IN_A/IN_B EQ1 control setting the midfrequency

boost and IN_A/IN_B EQ2 control setting the high frequency

boost. The IN_A/IN_B EQx control registers are ordered such

that Bit 5 is a sign bit, and midlevel boost is centered on 0x00;

setting Bit 5 low and increasing the LSBs results in decreasing

boost, while setting Bit 5 high and increasing the LSBs results in

increasing boost. The EQ CTL SRC bit (Bit 6) in the IN_A/IN_B

EQ1 control registers determines whether the equalization

control for the channel of interest is selected from the optimized

map or directly from the IN_A/IN_B EQx control registers (per

port). Setting this bit high selects equalization control directly

from the IN_A/IN_B EQx control registers, and setting it low

selects equalization control from the selected optimized map.

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