TDA10085HT datasheet(3/16 Pages) PHILIPS

3 / 16 page

2001 Aug 31

Philips Semiconductors

Product speciﬁcation

Single chip DVB-S/DSS channel receiver

TDA10085HT

FEATURES

• DSS and DVB-S compliant single chip demodulator and

forward error correction

• Dual 6-bit Analog-to-Digital Converter (ADC) on-chip

• PLL that allows using a low-cost crystal

(typically 4 MHz)

• DiSEqC 1.X from 1 to 8 byte-long sequences with

modulated or unmodulated output

• DSS dish control

• Digital cancellation of ADC offset

• Simultaneous parallel and serial output interfaces

• Variable rate BPSK/QPSK coherent demodulator

• Modulation rate variable from 1 to 49 Mbauds

• Automatic gain control output

• Digital symbol timing recovery:

– Acquisition range up to 960 ppm

• Carrier offset cancellation up to one half of the sampling

frequency

• Digital carrier recovery:

– Acquisition range up to 12% of the symbol rate

• Half-Nyquist filters: roll-off = 0.35 for DVB and

0.2 for DSS

• Interpolating and anti-aliasing filters to handle variable

symbol rates

• Channel quality estimation

• Spectral inversion ambiguity resolution

• Viterbi decoder:

– Supported rates from 1/2 to 8/9

– Constraint length K = 7 with G1 = 1718 and

G2 = 1338

– Viterbi output BER measurement

– Automatic code rate search within 1/2, 2/3 and 6/7 in

DSS mode

– Automatic code rate search within 1/2, 2/3, 3/4, 5/6

and 7/8 in DVB-S mode

• Convolutional de-interleaver and Reed Solomon

decoder according to DVB and DSS specifications

• Automatic frame synchronization

• Selectable DVB-S descrambling

• I2C-bus interface

• 64-pin TQFP package

• CMOS technology (0.2 µm, 1.8 V to 3.3 V).

APPLICATIONS

• DVB-S receivers (ETS 300-421)

• DSS receivers.

GENERAL DESCRIPTION

The TDA10085 is a single-chip channel receiver for

satellite television reception matching both DSS and

DVB-S standards. The device contains a dual 6-bit flash

ADC, variable rate BPSK/QPSK coherent demodulator

and forward error correction functions. The ADC interfaces

directly with I and Q analog baseband signals.

After analog-to-digital conversion, the TDA10085

implements a bank of cascadable filters as well as

anti-alias and half-Nyquist filters. An analog AGC signal is

generated using an amplitude estimation function. The

TDA10085 performs clock recovery at twice the baud rate

and achieves coherent demodulation without any

feedback to the local oscillator. Forward error correction is

built around two error-correcting codes: a Reed-Solomon

(outer code) and a Viterbi decoder (inner code). The

Reed-Solomon decoder corrects up to 8 erroneous bytes

among the N (204) bytes of one data packet.

A convolutional de-interleaver is located between the

Viterbi output and the Reed-Solomon decoder input. The

de-interleaver and Reed-Solomon decoder are

automatically synchronized according to a frame

synchronization algorithm that uses the sync pattern

present in each packet. The TDA10085 is controlled via an

I2C-bus interface. The circuit operates at sampling

frequencies up to 100 MHz, can process variable

modulation rates and achieves transmission rates up to

45 Mbaud. Furthermore, for dish control applications,

hardware supports DiSEqc 1.x with control access via the

I2C-bus.

An interrupt line that can be programmed to activate on

events or on timing information is provided.

Designed in 20 micron CMOS technology and housed in a

TQFP64 package, the TDA10085 operates over the

commercial temperature range.

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