Analog Frequency Multiplier

PL560-xx VCXO Family

47745 Fremont Blvd., Fremont, CA 94538 TEL (510) 492-0990, FAX (510) 492-0991

www.phaselink.com

Rev.:02-09-07 Page 2

O s c illa to r

A m p lif ie r

O E

Q

Q B A R

F r e q u e n c y

X 2

X IN

X O U T

L 2 X

V C O N

F r e q u e n c y

X 4

L 4 X

O n ly r e q u ir e d in x 4 d e s ig n s

Figure 2: Block Diagram of VCXO AFM

Figure 3 shows the period jitter histogram of the 2x Analog Frequency Multiplier at 311.04 MHz, while Figure 4 shows the very

low rejection levels of sub-harmonics that correspond to the exceptionally low jitter performance.

Figure 3: Period Jitter Histogram at 311.04 MHz

Figure 4: Spectrum Analysis at 311.04 MHz

Analog Frequency Multiplier (2x)

Analog Frequency Multiplier (2x)

with 155.52MHz crystal

with sub-harmonics below –72 dBc

OE LOGIC SELECTION

OUTPUT

OESEL

OE

Output State

0 (Default)

Enabled

0 (Default)

1

Tri-state

0

Tri-state

PECL

1

1 (Default)

Enabled

0

Tri-state

0 (Default)

1 (Default)

Enabled

0 (Default)

Enabled

LVDS or CMOS

1

1

Tri-state

OESEL and OE: Connect to VDD to set to “1”, connect to GND to set to “0”. Internally set to default through pull-down / -up.