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LTC2415-1IGN Datasheet(PDF) 27 Page - Linear Technology |
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LTC2415-1IGN Datasheet(HTML) 27 Page - Linear Technology |
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27 / 40 page  LTC2415/LTC2415-1 27 sn2415 24151fs APPLICATIO S I FOR ATIO Figure 18. LTC2415/LTC2415-1 Equivalent Analog Input Circuit Figure 19. An RC Network at IN+ and IN– Figure 21. –FS Error vs RSOURCE at IN + or IN– (Small CIN) Figure 20. +FS Error vs RSOURCE at IN+ or IN– (Small CIN) IIN VV V R IIN VV V R I REF VV V R V VR I REF VV V R V VR where AVG IN INCM REFCM EQ AVG IN INCM REFCM EQ AVG REF INCM REFCM EQ IN REF EQ AVG REF INCM REFCM EQ IN REF EQ + − + − () = +− • () = −+ − • () = •− + • − • () = −• − + • + • 05 05 15 05 15 05 2 2 . . . . . . :: . . ./ . V REF REF V REF REF VIN IN V IN IN R M INTERNAL OSCILLATOR Hz Notch F LOW R M INTERNAL OSCILLATOR Hz Notch F HIGH R f EXTERNAL OSCILLATOR R REF REFCM IN INCM EQ O EQ O EQ EOSC EQ =− = + =− = − == () == () =• () = +− +− +− +− 2 2 361 60 432 50 0 555 10 397 12 Ω Ω LTC2415 LTC2415 M M INTERNAL OSCILLATOR Hz Hz Notch F LOW O Ω 50 60 / = () LTC2415-1 CIN 2415 F19 VINCM + 0.5VIN RSOURCE IN+ LTC2415/ LTC2415-1 CPAR ≅20pF CIN VINCM – 0.5VIN RSOURCE IN – CPAR ≅20pF RSOURCE (Ω) 1 10 100 1k 10k 100k 2415 F20 50 40 30 20 10 0 VCC = 5V REF+ = 5V REF – = GND IN+ = 5V IN– = 2.5V FO = GND TA = 25°C CIN = 0.01µF CIN = 0.001µF CIN = 100pF CIN = 0pF RSOURCE (Ω) 1 10 100 1k 10k 100k 2415 F21 0 –10 –20 –30 –40 –50 VCC = 5V REF+ = 5V REF – = GND IN+ = GND IN– = 2.5V FO = GND TA = 25°C CIN = 0.01µF CIN = 0.001µF CIN = 100pF CIN = 0pF VREF+ VIN+ VCC RSW (TYP) 20k ILEAK ILEAK VCC ILEAK ILEAK VCC RSW (TYP) 20k CEQ 18pF (TYP) RSW (TYP) 20k ILEAK IIN+ VIN– IIN– IREF+ IREF– 2415 F18 ILEAK VCC ILEAK ILEAK SWITCHING FREQUENCY fSW = 76800Hz INTERNAL OSCILLATOR (LTC2415) (FO = LOW OR HIGH) fSW = 69900Hz INTERNAL OSCILLATOR (LTC2415-1) (FO = LOW) fSW = 0.5 • fEOSC EXTERNAL OSCILLATOR VREF– RSW (TYP) 20k incomplete settling of the input signal sampling process may result in gain and offset errors, but it will not degrade the INL performance of the converter. Figure 18 shows the mathematical expressions for the average bias currents flowing through the IN+ and IN– pins as a result of the sampling charge transfers when integrated over a sub- stantial time period (longer than 64 internal clock cycles). The effect of this input dynamic current can be analyzed using the test circuit of Figure 19. The CPAR capacitor includes the LTC2415/LTC2415-1 pin capacitance (5pF typical) plus the capacitance of the test fixture used to obtain the results shown in Figures 20 and 21. A careful implementation can bring the total input capacitance (CIN + CPAR) closer to 5pF thus achieving better performance than the one predicted by Figures 20 and 21. For simplic- ity, two distinct situations can be considered. |
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