24LC32

DS21072G-page 10

 2004 Microchip Technology Inc.

7.0

PIN DESCRIPTIONS

7.1

A0, A1, A2 Chip Address Inputs

The A0..A2 inputs are used by the 24LC32 for multiple

device operation and conform to the two-wire bus stan-

dard. The levels applied to these pins define the

address block occupied by the device in the address

map. A particular device is selected by transmitting the

corresponding bits (A2, A1, A0) in the control byte

(Figure 3-3).

7.2

SDA Serial Address/Data Input/Output

This is a bidirectional pin used to transfer addresses

and data into and data out of the device. It is an open

drain terminal, therefore the SDA bus requires a pullup

Ω for 100 kHz, 2 KΩ for

400 kHz)

For normal data transfer SDA is allowed to change only

during SCL low.

Changes during SCL high

are

reserved for indicating the START and STOP condi-

tions.

7.3

SCL Serial Clock

This input is used to synchronize the data transfer from

and to the device.

FIGURE 7-1:

CACHE WRITE TO THE ARRAY STARTING AT A PAGE BOUNDARY

FIGURE 7-2:

CACHE WRITE TO THE ARRAY STARTING AT A NON-PAGE BOUNDARY

1 Write command initiated at byte 0 of page 3 in the array;

First data byte is loaded into the cache byte 0.

2 64 bytes of data are loaded into cache.

3 Write from cache into array initiated by STOP bit.

Page 0 of cache written to page 3 of array.

Write cycle is executed after every page is written.

4 Remaining pages in cache are written

to sequential pages in array.

cache

byte 0

cache

byte 1

• • •

cache

byte 7

cache page 1

bytes 8-15

• • •

page 0

cache page 2

bytes 16-23

cache page 7

bytes 56-63

page 1 page 2

• • •

byte 7

• • •

page 4

• • •

page 7

page 3

cache page 0

Last page in cache written to page 2 in next row.

5

array row n

array row n + 1

page 0 page 1 page 2

byte 0

byte 1

page 4

page 7

1 Write command initiated; 64 bytes of data

loaded into cache starting at byte 2 of page 0.

2 Last 2 bytes loaded 'roll over'

to beginning.

3

Last 2 bytes

loaded into

page 0 of cache.

4 Write from cache into array initiated by STOP bit.

Page 0 of cache written to page 3 of array.

Write cycle is executed after every page is written.

cache

byte 1

cache

byte 2

• • •

cache

byte 7

cache page 1

bytes 8-15

• • •

page 0

cache page 2

bytes 16-23

cache page 7

bytes 56-63

page 1 page 2

• • •

• • •

page 4

• • •

page 7

page 3

Remaining bytes in cache are

written sequentially to array.

5

array

row n

array

row

n + 1

cache

byte 0

Last 3 pages in cache written to next row in array.

6

page 1 page 2

byte 0

byte 2

byte 1

page 4

page 7

byte 7

byte 3

byte 4

page 0