1999 Jan 12

13

Philips Semiconductors

Preliminary specification

10-bit high-speed low-power ADC with

internal reference regulator

TDA8764

Notes

1. In addition to a good layout of the digital and analog ground, it is recommended that the rise and fall times of the clock

must not be less than 0.5 ns.

2. The input admittance is

3. Analog input voltages producing code 0 up to and including code 1023:

4. In order to ensure the optimum linearity performance of such converter architecture the lower and upper extremities

of the converter reference resistor ladder (corresponding to output codes 0 and 1023 respectively) are connected to

a) The current flowing into the resistor ladder is

and the full-scale input range at the converter,

to cover code 0 to code 1023, is

will be kept reasonably constant from device to device. Consequently variation of the output

supply voltage. When several ADCs are connected in parallel and fed with the same reference source, the

matching between each of them is then optimized.

5.

6. The analog bandwidth is defined as the maximum input sine wave frequency which can be applied to the device.

No glitches greater than 2 LSBs, nor any significant attenuation are observed in the reconstructed signal.

7. The analog input settling time is the minimum time required for the input signal to be stabilized after a sharp full-scale

input (square wave signal) in order to sample the signal and obtain correct output data.

8. Effective bits are obtained via a Fast Fourier Transform (FFT) treatment taking 8 K acquisition points per equivalent

fundamental period. The calculation takes into account all harmonics and noise up to half of the clock frequency

(NYQUIST frequency). Conversion to signal-to-noise ratio: SINAD = EB

× 6.02 + 1.76 dB.

9. Intermodulation measured relative to either tone with analog input frequencies of 5 and 5.1 MHz. The two input

signals have the same amplitude and the total amplitude of both signals provides full-scale to the converter.

it is recommended to have the lowest possible output load.

V

i

1

R

i

-----

Cijw

+





=

I

L

V

RT

V

RB

–

R

OB

R

L

R

OT

++

------------------------------------------

=

V

I

R

L

I

L

×

R

L

R

OB

R

L

R

OT

++

------------------------------------------

V

RT

V

RB

–

()

0.866

V

RT

V

RB

–

()

×

=

×

=

=

R

L

R

OB

R

L

R

OT

++

------------------------------------------

E

G

V

1023

V

0

–

() V

ip

p

–

()

–

V

ip

p

–

()

------------------------------------------------------------

100

×

=