MP6543 – 12V, 2A, THREE-PHASE POWER STAGE

MP6543 Rev. 1.01

www.MonolithicPower.com

13

1/15/2020

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© 2020 MPS. All Rights Reserved.

OPERATION

The MP6543 is a three-channel half-bridge driver

intended to drive a brushless DC motor.

Input Logic

The MP6543 has logic input pins ENA, ENB, and

ENC, which enable the outputs SA, SB, and SC.

When ENx is low, the corresponding output is

disabled (output is high-impedance), and the

PWM input on that phase is ignored. When ENx

is high, the output is enabled, and the PWM input

controls the state of the output. Table 1.1 shows

the logic truth table.

Table 1.1: Input Logic Truth Table of the MP6543

ENx

PWMx

Sx

H

H

VIN

H

L

GND

L

X

High impedance

The MP6543A has separate inputs to enable the

HS-FETs

and

LS-FETs

of

each

phase

independently. Table 1.2 shows the logic truth

table.

Table 1.2: Input Logic Truth Table of the MP6543A

HSx

LSx

Sx

L

L

High impedance

L

H

GND

H

L

VIN

H

H

High impedance

The MP6543B has three Hall-element inputs,

whose commutation logic is determined by three

Hall-element inputs spaced at 120°. The PWM,

DIR, and nBRAKE inputs control motor speed,

direction, and brake engagement, respectively.

Table 1.3: Input Logic Truth Table of the MP6543B

PWM

nBRAKE

Operation Mode

0

1

PWM chop mode – the load

current decays

0

0

Brake mode – all low-side

gates on

1

1

Selected drivers on

1

0

Brake mode – all low-side

gates on

Table 2: Commutation Table of the MP6543B

(nBRAKE = 1)

Logic Inputs

Motor Terminals

HA

HB

HC

DIR

SA

SB

SC

1

0

1

1

PWM

Z

L

1

0

0

1

Z

PWM

L

1

1

0

1

L

PWM

Z

0

1

0

1

L

Z

PWM

0

1

1

1

Z

L

PWM

0

0

1

1

PWM

L

Z

1

0

1

0

L

Z

PWM

0

0

1

0

L

PWM

Z

0

1

1

0

Z

PWM

L

0

1

0

0

PWM

Z

L

1

1

0

0

PWM

L

Z

1

0

0

0

Z

L

PWM

0

0

0

X

Z

Z

Z

1

1

1

X

Z

Z

Z

Note that the logic inputs have internal weak pull-

down resistors.

nSLEEP Operation

Driving nSLEEP low puts the device into a low-

power sleep state. In this state, all internal

circuits are disabled. All inputs are ignored when

nSLEEP is active low. When waking up from

sleep mode, approximately 1.5ms must pass

before the device responds to inputs. The

nSLEEP input has a weak pull-down resistor.

Current-Sense Amplifiers

The current flowing in each of the three outputs is

sensed by internal current-sensing circuits. An

output pin for each phase sources or sinks a

current that is proportional to the current flowing

in each phase. Note that only current flowing in

the LS-FET is sensed, and that it is sensed in

both the forward and reverse directions.

To convert this current into a voltage (e.g. to

input to an A/D converter), a termination resistor

(RREF) is used as a reference voltage. When

there is no current flowing, the resultant output

will be equal to the reference voltage. When

current is flowing, the voltage is above or below

the reference voltage, determined with Equation

(1):

VSOUT = VREF + (RREF * ILOAD) / 4000

(1)