UMA1002 datasheet(4/36 Pages) PHILIPS

4 / 36 page

1997 Jan 28

Philips Semiconductors

Product speciﬁcation

Data processor for cellular radio

(DPROC2)

UMA1002

PINNING

SYMBOL

DESCRIPTION

SO28

LQFP32

VSSA

Negative analog supply (0 V). To be connected low-ohmic to VSSD.

AGND

Internally generated analog signal ground. Voltage level = 1

⁄2VDDA. This pin should

be connected to a blocking capacitor, no DC load allowed.

DEMODD

DEMODD inputs analog data and SAT signals from the RF demodulator. This pin

should normally be AC-coupled. See Chapter “AC characteristics”.

DATA

Data is an analog output which provides the Manchester encoded and filtered data

signal, SAT and signalling tone. This signal should normally be AC-coupled into the

Audio/Data summer. See Chapter “AC characteristics”.

RACTRL

Received audio control output. Open-drain output used to blank the audio path to

the earpiece when a sequence of dotting followed by a synchronization word or 2

synchronization words separated by 77 bits is detected. RACTRL and TACTRL

functions can be combined using one line. Output level LOW means audio muted.

RESET

Master reset input resetting all internal ﬂip-ﬂops to the speciﬁed state. This input

has no inﬂuence on analog parts, but must be controlled by an active HIGH

microcontroller port.

INVRX

This input inverts the sense of received data stream, which allows RF

demodulators with high or low local oscillators to be used. The AMPS and TACS

speciﬁcations deﬁne NRZ encoded logic 1 as a LOW-to-HIGH transition in the

centre of a data bit period. The polarity of the demodulated data stream into

DPROC2 depends on the receiver local oscillator. Input LOW means data normal.

RXLINE

Received data signal output to the system controller.

TST

Test input pin (note 1).

RECDATA

Output of the recovered digital data signal (note 1).

TACTRL

Transmitter audio control output. This open-drain output is used to blank the audio

path and enable the data path to the modulator during data bursts on the RVC.

Output level LOW means audio muted.

CLKIN

1.2 MHz or 9.6 MHz external master clock input. This input signal should be

accurate to 100

× 10−6 and have a worst case 60 : 40 mark-space ratio.

CLKOUT

Output of 1.2 MHz clock signal (for APROC) derived from CLKIN.

VSSD

Negative digital supply (0 V), internally connected to substrate. To be connected

low-ohmic to VSSA.

TXLINE

Open-drain bidirectional data line to the system controller (internal 100 k

Ω pull-up).

n.c.

Not connected.

TXHOLD

This input holds off transmission of data when set to HIGH.

TXCLK

Transmitted data clock input from the system controller.

BUSY/VSAT

Output indicating the status of the RECC by providing output information based on

a majority decision on the last 3 consecutive Busy/Idle bits (FVC = logic 0). Output

level LOW means channel idle.

Indicating the result of the comparison of the measured SAT and the expected SAT

colour-code bits (I2C-bus register) in the voice channel mode (FVC = logic 1 and

ENSM = logic 1). Output level LOW means incoming SAT not equal to expected

SAT.

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