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CS8420-CS Datasheet(PDF) 65 Page - Cirrus Logic |
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CS8420-CS Datasheet(HTML) 65 Page - Cirrus Logic |
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65 / 94 page ![]() DS245F4 65 CS8420 13.4.1 Pin Description - Hardware Mode 3 Overall Device Control: DFC0, DFC1 - Data Flow Control Inputs DFC0 and DFC1 inputs determine the major data flow options available in Hardware mode, according to Table 5. OMCK - Output Section Master Clock Input Output section master clock input. The frequency must be 256x the output sample rate (Fso). Audio Input Interface: SDIN - Serial Audio Input Port Data Input Audio data serial input pin. This data will be transmitted out the AES3 port. ISCLK - Serial Audio Input Port Bit Clock Input Serial bit clock for audio data on the SDIN pin. ILRCK - Serial Audio Input Port Left/Right Clock Input Word rate clock for the audio data on the SDIN pin. The frequency will be at the output sample rate (Fso) Audio Output Interface: SDOUT - Serial Audio Output Port Data Output Audio data serial output pin. This is also a start-up option pin, and requires a pull-up or pull-down resistor. OSCLK - Serial Audio Output Port Bit Clock Input or Output Serial bit clock for audio data on the SDOUT pin. |
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