ICS9212-13 datasheet(1/7 Pages) ICST

Part #	ICS9212-13

Description	Direct Rambus??Clock Generator

PDF	7 Pages

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Manufacturer	ICST [Integrated Circuit Systems]

Direct Link	http://www.icst.com

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1 / 7 page

Integrated

Circuit

Systems, Inc.

General Description

Features

ICS9212-13

0272F—08/08/07

Block Diagram

Direct Rambus™ Clock Generator

Pin Configuration

The ICS9212-13 is a High-speed clock generator providing

up to 600 MHz differential clock source for direct Rambus

™

memory system. It includes DDLL (Distributed Delay

locked loop) and phase detection mechanism to

synchronize the direct Rambus

™ channel clock to an

external system clock. ICS9212-13 provides a solution for

a broad range of Direct Rambus memory applications. The

device works in conjunction with the ICS9250-09.

The ICS9212-13 power management support system

turns “off” the Rambus

™ channel clock to minimize power

consumption for mobile and other power–sensitive

applications. In “clock off” mode the device remains “on”

while the output is disabled, allowing fast transitions

between clock-off and clock–on states. In “power down”

mode it completely powers down for minimum power

dissipation.

The ICS9212-13 meets the requirements for input frequency

tracking when the input frequency clock is using Spread

Spectrum clocking and also the optimum bandwidth is

maintained while attenuating the jitter of the reference

signal.

24-Pin 150 Mil SSOP

•

Compatible with all Direct Rambus™ based IC s

•

Up to 600 MHz differential clock source for direct

Rambus™ memory system

•

Cycle to cycle jitter is less than 40ps

•

3.3 + 5% supply

•

Synchronization flexibility: Supports Systems that

need clock domains of Rambus channel to

synchronize with system or processor clock, or

systems that do not require synchronization of the

Rambus clock to another system clock

•

Excellent power management support

•

REFCLK input is from the ICS9250-09.

BUSCLK_STOP#

PLL

Phase

Aligner

Pclk/M

Multi(0:1)

Synclk/N

PD#

FS(0:1)

Refclk

Test MUX

Bypass MUX

Bypclk

PLLclk

GND

2

PAclk

BUSCLKT

BUSCLKC

B

A

Phase

Detector

VDDREF

REFCLK

VDD1

GND1

GND3

PCLK/M

SYNCLK/N

GND2

VDD2

VDDPD

BUSCLK_STOP#

PD#

FS0

FS1

VDD-OUT

GND-OUT

BUSCLKT

N/C

BUSCLKC

GND-OUT

VDD-OUT

MULTI0

MULTI1

FS2

1

2

3

4

5

6

7

8

9

10

11

12

24

23

22

21

20

19

18

17

16

15

14

13

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