 |
Electronic Components Datasheet Search |
|
|
Electronic Components Datasheet Search |
|
ADC3908CSSS Datasheet(PDF) 29 Page - Texas Instruments |
|
|
|||||||||||||||||||||||||||||
ADC3908CSSS Datasheet(HTML) 29 Page - Texas Instruments |
|
|
29 / 47 page  7.3.3.2 Interface Configuration using Pin Control The ADC3908Dx and ADC3908Sx analog input and output interface is configured via pin control only. Pins M0, M1, and M2 can either be pulled high to AVDD, pulled low to GND or intermediate voltages in between. Interface Configuration Table shows configuration options. Table 7-2. Interface Configuration Pin Name Description GND 0.5V 1V AVDD M0 CMOS interface DDR (dual channel only) SDR (single channel only) M1 Output data ADC data Test Pattern M2 Analog input Differential input Single-ended input Output data format 2's Complement Offset binary 2's Complement Offset binary www.ti.com ADC3908D025, ADC3908D065, ADC3908D125 ADC3908S025, ADC3908S065, ADC3908S125 SBASAU9 – OCTOBER 2024 Copyright © 2024 Texas Instruments Incorporated Submit Document Feedback 29 Product Folder Links: ADC3908D025 ADC3908D065 ADC3908D125 ADC3908S025 ADC3908S065 ADC3908S125 |
|
Link URL |
| Does ALLDATASHEET help your business so far? [ DONATE ] |
About Alldatasheet | Advertisement | Contact us | Privacy Policy | Link to Datasheet | Link Exchange | Manufacturer List All Rights Reserved©Alldatasheet.com |
| Russian : Alldatasheetru.com | Korean : Alldatasheet.co.kr | Spanish : Alldatasheet.es | French : Alldatasheet.fr | Italian : Alldatasheetit.com Portuguese : Alldatasheetpt.com | Polish : Alldatasheet.pl | Vietnamese : Alldatasheet.vn Indian : Alldatasheet.in | Mexican : Alldatasheet.com.mx | British : Alldatasheet.co.uk | New Zealand : Alldatasheet.co.nz |
|
Family Site : ic2ic.com |
icmetro.com |
British ▼
English
Chinese
German
Japanese
Russian
Korean
Spanish
French
Italian
Portuguese
Polish
Vietnamese
Indian
Mexican
British
New Zealand
