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Design Features

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Package size: 2 x 3 mm2 - 33 x 28 mm2

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Package thickness: 0.275 mm (WLSiP – Multi-chip

module) to 1.900 mm (WL3D)

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WLSiP with up to 10 active dies and 50 passives

qualified

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Minimum through package via pitch: 0.350 mm

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BGA pitch: down to 0.350 µm

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Minimum die-to-die distance: 0.100 mm

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Minimum passive-to-die and passive-to-passive

distance: 0.150 mm

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Minimum die TPV pad pitch: 0.050 mm and

opening 0.045 mm

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Bottom side Cu-RDL minimum line/space:

0.010 mm/0.010 mm, multi-layer RDL

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Top side Cu-RDL minimum line/space:

0.020 mm/0.020 mm, single-layer RDL

WLSiP & WL3D

Differentiation

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High integration density through small die-to-die

distance

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Multi-layer RDL and double-sided RDL (WLFO

bottom and top side)

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3D stacking enabled by TPV concept

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Small form factor (optimization based on customer

needs in footprint or z-height)

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BGA ball attach and flip chip with underfill assembly

on same WLFO bottom side

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Heterogeneous integration of multiple different

active dies (Si, GaAs, SiGe), already packaged dies,

passives, optical elements, sensors and MEMS

Cross Sections

WLFO-Based Embedded Wafer Level System Integration Portfolio

WLSiP passives integration

WLSiP multi-chip module

WL3D face-to-face

WL3D RDL on both sides

through package vias

WLSiP multi-chip module

WL3D Package-on-Package,

face-to-face, through package vias

Dual die package

pick & place

WLSiP before molding

WLSiP after molding

Cross section

through package vias