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POWER MANAGEMENT

SC2621

Applications Information

THEOR

THEOR

THEOR

THEOR

THEORY OF OPERA

Y OF OPERA

Y OF OPERA

Y OF OPERA

Y OF OPERATION

TION

TION

TION

TION

The SC2621 integrates a high-speed, voltage mode PWM

controller with a linear controller into a single package. It

is designed to control two independent output voltages

for high performance graphic card applications.

As shown in the block diagram of the SC2621, the volt-

age-mode PWM controller consists of an error amplifier,

a 500kHz ramp generator, a PWM comparator, a RS latch

circuit, and two MOSFET drivers. The buck converter out-

put voltage is fed back to the error amplifier negative

input and is regulated to a reference voltage level. The

error amplifier output is compared with the ramp to gen-

erate a PWM wave, which is amplified and used to drive

the MOSFETs in the buck converter. The PWM wave at

the phase node with the amplitude of Vin is filtered out

to get a DC output. The linear controller is an error ampli-

fier. It provides the gate drive and output voltage control

for a linear regulator. Both PWM controller and linear con-

troller work with soft-start and fault monitoring circuitry

to meet application requirement.

UVLO, Start Up and Shut Down

UVLO, Start Up and Shut Down

UVLO, Start Up and Shut Down

UVLO, Start Up and Shut Down

UVLO, Start Up and Shut Down

To initiate the SC2621, a supply voltage is applied to Vcc

pin. The top gate (DH) and bottom gate (DL) are held low

until Vcc voltage exceed UVLO (Under Voltage Lock Out)

threshold, typically 4.0V. Then the internal Soft-Start (SS)

capacitor begins to charge, the top gate remains low,

and the bottom gate is pulled high to turn on the bottom

MOSFET. When the SS voltage at the capacitor reaches

0.4V, the linear controller is enabled and LDO output is

turned on. Meanwhile, the top and bottom gates of PWM

controller begin to switch. The switching regulator output

is slowly ramping up for a soft turn-on.

If the supply voltages at Vcc pin falls below UVLO thresh-

old during a normal operation, the SS capacitor begins

to discharge. When the SS voltage reaches 0.4V, the

PWM controller controls the switching regulator output

to ramp down slowly for a soft turn-off. Meanwhile, the

linear controller is disabled and LDO output is turned off.

Hiccup Mode Short Circuit Protection

Hiccup Mode Short Circuit Protection

Hiccup Mode Short Circuit Protection

Hiccup Mode Short Circuit Protection

Hiccup Mode Short Circuit Protection

over current protection. In every switching cycle, after

the bottom MOSFET is on for 150ns, the SC2621 de-

tects the phase node voltage and compares it with an

internal setting voltage. If the phase node is lower than

the setting voltage, an overcurrent condition occurs. The

SC2621 will discharge the internal SS capacitor and shut-

down both outputs. After waiting for around 10 millisec-

onds, the SC2621 begins to charge SS capacitor again

and initiates a fresh startup. The startup and shutdown

cycle will repeat until the short circuit is removed. This is

called a hiccup mode short circuit protection.

To program a load trip point for short circuit protection, it

is recommended to connect a 3.3k resistor from the OCS

the DRV pin, as shown in Fig. 1.

SC2621

GND

OCS

DRV

VCC

11

4

9

3.3k

Rset

12V

8

Fig. 1. Programming load trip point

node voltage Vpn at the load trip point. This voltage is

the product of the inductor peak current at the load trip

on

_

ds

peak

pn

R

I

V

´

=

The soft start time of the SC2621 is fixed at around 5ms.

Therefore, the maximum soft start current is determined

by the output inductance and output capacitance. The

values of output inductor and output bulk capacitors have

to be properly selected so that the soft start peak cur-

rent does not exceed the load trip point of the short cir-

cuit protection.

Internal LDO for Gate Drive

Internal LDO for Gate Drive

Internal LDO for Gate Drive

Internal LDO for Gate Drive

Internal LDO for Gate Drive

An internal LDO is designed in the SC2621 to lower the

12V supply voltage for gate drive. An 1uF external ce-

ramic capacitor connected in between DRV pin to the

ground is needed to support the LDO. The LDO output is

connected to low gate drive internally, and has to

beconnected to high gate drive through an external boot-

strap circuit. The LDO output voltage is set at 8.2V.