9

 2004 Semtech Corp.

www.semtech.com

SC4611

POWER MANAGEMENT

Applications Information (Cont.)

The classical Type III compensation network can be built

around the error amplifier as shown below

Figure 1. Voltage Mode Buck Converter Compensation

Network

The transfer function of the compensation network is as

follows:

where,

0dB

Gd

T

ω

Z2

p1

p2

c

ESR

ω

ω

ω

ω

Loop gain T(s)

The design guidelines are as following:

1. Set the loop gain crossover frequency w

switching frequency.

2. Place an integrator in the origin to increase DC and low

frequency gains.

3. Select w

dampen peaking; the loop gain has –20 dB rate to go

across the 0 dB line for obtaining a wide bandwidth.

4. Cancel w

5. Place a high frequency compensation pole w

the switching frequency to get the maximum attenuation

of the switching ripple and the high frequency noise with

the adequate phase lag at w

PCB LA

PCB LA

PCB LA

PCB LA

PCB LAYYYYYOUT F

OUT F

OUT F

OUT F

OUT FOR SC46

OR SC46

OR SC46

OR SC46

OR SC461

11

1

11

11

1

1

Careful attention to layout requirements is necessary for

successful implementation of the SC4611 PWM controller.

High switching currents with fast rise and fall times are

present in the application and their effect on ground plane

voltage differentials must be understood and minimized.

A good layout with minimum parasitic loop areas will

a) reduce EMI

b) lower ground injection currents, resulting in electrically

“cleaner” grounds for the rest of the system and

c) minimize source ringing, resulting in more reliable gate

switching signals.

LA

LA

LA

LA

LAYYYYYOUT GUIDELINES

OUT GUIDELINES

OUT GUIDELINES

OUT GUIDELINES

OUT GUIDELINES

In the following Q

side MOSFETs respectively.

1) A ground plane should be used. The number and position

of ground plane interruptions should be minimised so as

not to compromise ground plane integrity. Isolated or semi-

isolated areas of the ground plane may be deliberately

introduced to constrain ground currents into particular

paths, such as the output capacitor or the Q

)

1

)(

1

(

)

1

)(

1

(

)

(

2

1

2

1

P

P

Z

Z

I

COMP

s

s

s

s

s

s

G

ω

ω

ω

ω

ω

+

+

+

+

⋅

=

2

3

1

2

1

2

1

)

(

1

,

1

C

R

R

C

R

Z

Z

+

=

=ω

ω

3

1

3

1

2

2

2

3

1

3

1

1

1

,

1

,

)

(

1

C

C

C

C

R

C

R

C

C

R

P

P

I

+

=

=

+

=ω

ω

ω

R3

C3

R2

R1

C1

Vref

C2

-

+

Figure 2. Simplified asymptotic diagram of buck power

stage and its compensated loop gain.