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MX98726EC Datasheet(PDF) 2 Page - Macronix International |
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MX98726EC Datasheet(HTML) 2 Page - Macronix International |
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2 / 56 page  2 P/N:PM0729 REV. 1.1, MAY. 28, 2001 MX98726EC 1.2 Internal Block Diagram Packet Buffer (SRAM) SRAMIU RX FIFO RX SM Host BIU TX FIFO TX SM PCS Architecture and Interface overview 100 TX PHY 100TX PMD interface NWAY CTRL & REGS 10Mbps MCC+TP interface EPROM MII Interface Serial ROM port 1.3 Typical Applications uP with dedicate bus MX98726EC Packet buffer Customer Application Interleaved memory Architecture TP cable RJ45 Xformer decode EPROM C46/C66 local DMA Host side CSB |
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