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SC1480ITSTRT Datasheet(PDF) 13 Page - Semtech Corporation |
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SC1480ITSTRT Datasheet(HTML) 13 Page - Semtech Corporation |
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13 / 22 page ![]() 13 2006 Semtech Corp. www.semtech.com SC1480 POWER MANAGEMENT Applications Information (Cont.) The error comparator offset is trimmed so that it trips when VOUT is 1.25 volts +/-1% at room temperature. This offset does not drift significantly with supply and temperature. Thus, the error comparator contributes 1% or less to DC system inaccuracy. The on pulse in the SC1480 is calculated to give a pseudo fixed frequency. Nevertheless, some frequency variation with line and load can be expected. This variation changes the output ripple voltage. Because constant on regulators regulate to the valley of the output ripple, ½ of the output ripple appears as a DC regulation error. For example, if REFOUT=1.25 volts, then the valley of the output ripple will be 1.25 volts. If the ripple is 20mv with VIN=6, then the DC output voltage will be 1.26 volts. If the ripple is 40mv with VIN=25 volts, then the DC output voltage will be 1.27 volts. The best way to minimize this effect is to minimize the output ripple. To compensate for valley regulation it is usually desirable to use passive droop. Take the feedback directly from the output side of the inductor incorporating a small amount of trace resistance between the inductor and output capacitor. This trace resistance should be optimized so that at full load the output droops to near the lower regulation limit. Passive droop minimizes the required output capacitance because the voltage excursions due to load steps are reduced. Passive droop also improves stability so it should be used when possible. Thermal Considerations The junction temperature of the device may be calculated as follows: C P T T JA D A J ° θ • + = Where: T A = ambient temperature (°C) P D = power dissipation in (W) θ JA = thermal impedance junction to ambient from absolute maximum ratings (°C/W) The power dissipation may be calculated as follows: W f Q V I VCCA P g g VCCA D • • + • = Where: VCCA = chip supply voltage (V) I VCCA = operating current (A) V g = gate drive voltage, typically 5V (V) Q g = FET gate charge, from the FET datasheet (C) f = switching frequency (kHz) Inserting the following values as an example: T A = 85°C θ JA = 100°C/W VCCA = 5V I VCCA = 1100µA (data sheet maximum) V g = 5V Q g = 60nC f = 300kHz gives us: () C 95 100 10 300 10 60 5 10 1100 5 85 T 3 9 6 J ° = • • • • • + • • + = − − As can be seen, the heating effects due to internal power dissipation are practically negligible, thus requiring no special consideration thermally during layout. |
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