SH3000 datasheet(3/24 Pages) SEMTECH

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SH3000 MicroBuddy™

SYSTEM MANAGEMENT

V1.15 www.semtech.com

Pin Descriptions

Name

Type

Function

VSS

Power

Ground, 0 V. All VSS pins and TEST (VSS) pin must be connected together.

VREG

Power

Output of internal Voltage Regulator, 2.2 V nominal. This pin can power external loads

of <5 mA. If load is “noisy” it requires a bypass capacitor. May be left unconnected or

used as a high logic level signal for CLKSEL pin (see below).

VDD

Power

Main power supply, +2.3 to +5.5 V.

VBAK

Power

Backup power supply for real time clock, +2.3 to +5.5 V (+1.8 to +5.5 V typical). This

voltage can be higher or lower than VDD. Connect a backup battery or backup

capacitor (with external recharge circuit). Connect to VDD if not used.

XIN

Analog In

XOUT

Analog Out

Oscillator pins for optional external low frequency crystal, typically 32.768 kHz watch

crystal with nominal 12.5 pF load capacitance. Keep open or connect to VSS if not

used.

CLKSEL

Digital In

A logic low level selects the internal 32 kHz RC oscillator (CLKSEL tied to VSS). A high

state on this pin selects the 32 kHz crystal oscillator (CLKSEL is connected to VREG).

The SH3000 always starts up using the internal 32 kHz RC oscillator. If CLKSEL is

high, the internal 32 kHz clock switches to the crystal oscillator once it has stabilized,

and RC oscillator is disabled for power conservation.

Do not connect CLKSEL to any signals except VSS or VREG. CLKSEL must not be left

open.

VSS

Power

Ground, 0 V. All VSS pins and TEST (VSS) pin must be connected together.

RREF

Analog

Optional 1MOhm external bias resistor for the internal 32 kHz RC oscillator. Can be

used to set, trim or modulate the internal RC oscillator. Keep open if not used.

RST

Digital Out

Active low system reset output. Asserted with a strong low state when a reset condition

occurs. Weakly pulled to VDD internally when not active. This signal is valid for VDD as

low as 1 V. Keep open if not used.

RST

Digital Out

Active high system reset output. Asserted with a strong high state when a reset

condition occurs. Weakly pulled to VSS internally when not active. This signal is valid

for VDD as low as 1 V. Keep open if not used.

12 TEST (VSS)

Digital In

Factory test enable. All VSS pins and TEST (VSS) pin must be connected together.

CLK32

Digital Out

Buffered internal 32 kHz clock, derived according to the CLKSEL pin setting. This pin

uses backup power for the buffer when VDD is not present. When driving high, this signal

is either at VBAK or VDD (if VDD is higher than the reset threshold). When enabled, this

signal runs continuously independent of CLKOUT activity. Minimize the external load to

reduce power consumption during backup operations. When disabled, this pin is driven

to VSS. Keep open if not used.

IO/INT

I/O

Serial communications interface and interrupt output pin. This pin is internally weakly

pulled to the opposite of the programmed interrupt polarity. For example, if interrupt is

programmed to be active low, this pin is weakly pulled to VDD when inactive. Keep

open if not used.

CLKIN

Digital In

Clock activity sense input. Used to detect when the target microcontroller enters stop

mode (which disables its clock). Connect to the microcontroller’s clock output or

oscillator output pin. Connect to VSS when not used. CLKIN must not be left open.

CLKOUT

Digital Out

Programmable high frequency clock output. Connect to the target microcontroller’s clock

input or oscillator input pin. Keep open if not used.

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